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AD7226BRSZ Datasheet, PDF (9/16 Pages) Analog Devices – LC2MOS Quad 8-Bit D/A Converter | |||
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AD7226
VREF
MSB
DB7
DAC A
DB0
LSB
DAC B
WR
DAC C
A1
A0
DAC D
VDD
VOUTA
VOUTB
VOUTC
VOUTD
VSS AGND
DGND
Figure 8. AD7226 Unipolar Output Circuit
Table II. Unipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output
1111
1111
+VREF ÃÃà 225565˯Ë
1000
0001
+V
REF
ÃÃÃ
129
256
˯Ë
1000
0000
+V REF
ÃÃà 122586˯Ë
=
+
V
REF
2
0111
1111
+V
REF
ÃÃÃ
127
256
˯Ë
0000
0001
+V
REF
ÃÃÃ
1
256
˯Ë
0000
0000
0V
( )( ) Note: LSB = VREF
2â8
= VREF
à 1Ë
Ãà 256¯Ë
(2)
Bipolar Output Operation
Each of the DACs of the AD7226 can be individually config-
ured to provide bipolar output operation. This is possible using
one external amplifier and two resistors per channel. Figure 9
shows a circuit used to implement offset binary coding (bipolar
operation) with DAC A of the AD7226. In this case
( ) ( ) VOUT
=
ÃÃÃ1 +
R2Ë
R1¯Ë
Â¥
DAVREF
â
Ã
ÃÃ
R2Ë
R1¯Ë
Â¥
VREF
(3)
With R1 = R2
( ) VOUT = 2DA â 1 Â¥VREF
(4)
where DA is a fractional representation of the digital word in latch A.
Mismatch between R1 and R2 causes gain and offset errors and
therefore these resistors must match and track over tempera-
ture. Once again the AD7226 can be operated in single supply
or from positive/negative supplies. Table III shows the digital
code versus output voltage relationship for the circuit of Figure 9
with R1 = R2.
VREF
VREF
AD7226*
DAC A
VSS AGND
R1
VDD
VOUTA
R2
+15V
VOUT
â15V
DGND
R1, R2 = 10kâ Ø0.1%
*DIGITAL INPUTS OMITTED
FOR CLARITY
Figure 9. AD7226 Bipolar Output Circuit
Table III. Bipolar (Offset Binary) Code Table
DAC Latch Contents
MSB
LSB
Analog Output
1111
1000
1111
0001
+VREF ÃÃÃ112287˯Ë
+V
REF
ÃÃÃ
1
128
˯Ë
1000
0111
0000
0000
0000
1111
0001
0000
0V
âV
REF
ÃÃÃ
1
128
˯Ë
âVREF ÃÃÃ112287˯Ë
âVREF ÃÃÃ112288ËÂ¯Ë = âVREF
AGND BIAS
The AD7226 AGND pin can be biased above system GND
(AD7226 DGND) to provide an offset âzeroâ analog output
voltage level. Figure 10 shows a circuit configuration to achieve
this for channel A of the AD7226. The output voltage, VOUTA,
can be expressed as:
( ) VOUT A = VBIAS + DA VIN
(5)
where DA is a fractional representation of the digital input word
(0 £ D £ 255/256).
REV. D
â9â
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