AD625_16 Datasheet, PDF (9/16 Pages) Analog Devices – Programmable Gain Instrumentation Amplifier

AD625
THEORY OF OPERATION
The AD625 is a monolithic instrumentation amplifier based on
a modification of the classic three-op-amp approach. Monolithic
construction and laser-wafer-trimming allow the tight matching
and tracking of circuit components. This insures the high level
of performance inherent in this circuit architecture.
A preamp section (Q1–Q4) provides additional gain to A1 and
A2. Feedback from the outputs of A1 and A2 forces the collec-
tor currents of Q1–Q4 to be constant, thereby, impressing the
input voltage across R_G. This creates a differential voltage at the
outputs of A1 and A2 which is given by the gain (2R_F/R_G + 1)
times the differential portion of the input voltage. The unity
gain subtracter, A3, removes any common-mode signal from the
output voltage yielding a single ended output, V_OUT, referred to
the potential at the reference pin.
The value of R_G is the determining factor of the transconduc-
tance of the input preamp stage. As R_G is reduced for larger
gains the transconductance increases. This has three important
advantages. First, this approach allows the circuit to achieve a
very high open-loop gain of (3 × 10⁸ at programmed gains ≥ 500)
thus reducing gain related errors. Second, the gain-bandwidth
product, which is determined by C3, C4, and the input trans-
conductance, increases with gain, thereby, optimizing frequency
response. Third, the input voltage noise is reduced to a value
determined by the collector current of the input transistors
(4 nV/√Hz).
INPUT PROTECTION
Differential input amplifiers frequently encounter input voltages
outside of their linear range of operation. There are two consid-
erations when applying input protection for the AD625; 1) that
continuous input current must be limited to less than 10 mA
and 2) that input voltages must not exceed either supply by
more than one diode drop (approximately 0.6 V @ 25°C).
Under differential overload conditions there is (R_G + 100) Ω in
series with two diode drops (approximately 1.2 V) between the
plus and minus inputs, in either direction. With no external protec-
tion and R_G very small (i.e., 40 Ω), the maximum overload
voltage the AD625 can withstand, continuously, is approximately
± 2.5 V. Figure 26a shows the external components necessary to
protect the AD625 under all overload conditions at any gain.
+V_S
+
50␮A
VB
–
50␮A
A1
C3
A2
C4
10k⍀
GAIN
DRIVE
GAIN
DRIVE
10k⍀
50⍀
–IN
Q1, Q3
R_F R_F
R_G
Q2, Q4
50⍀
50␮A
GAIN GAIN
SENSE SENSE
50␮A
10k⍀
10k⍀
+IN
SENSE
V_O
REF
–V_S
Figure 25. Simplified Circuit of the AD625
The diodes to the supplies are only necessary if input voltages
outside of the range of the supplies are encountered. In higher
gain applications where differential voltages are small, back-to-
back Zener diodes and smaller resistors, as shown in Figure
26b, provides adequate protection. Figure 26c shows low cost
FETs with a maximum ON resistance of 300 Ω configured to offer
input protection with minimal degradation to noise, (5.2 nV/√Hz
compared to normal noise performance of 4 nV/√Hz).
During differential overload conditions, excess current will flow
through the gain sense lines (Pins 2 and 15). This will have no
effect in fixed gain applications. However, if the AD625 is being
used in an SPGA application with a CMOS multiplexer, this
current should be taken into consideration. The current capa-
bilities of the multiplexer may be the limiting factor in allowable
overflow current. The ON resistance of the switch should be
included as part of R_G when calculating the necessary input
protection resistance.
+V_S
1.4k⍀
+IN
1.4k⍀
–IN
FD333 FD333
R_F
R_G
R_F
FD333 FD333
AD625
V_OUT
–V_S
Figure 26a. Input Protection Circuit
+VS
500⍀
+IN
FD333
FD333
1N5837A
RF
RG
1N5837A
RF
500⍀
–IN
FD333
AD625
VOUT
FD333
–VS
Figure 26b. Input Protection Circuit for G > 5
+VS
FD333
+IN
2k⍀
2N5952
FD333
RF
RG
AD625
RF
VOUT
–IN
2k⍀
2N5952
FD333
FD333
–VS
Figure 26c. Input Protection Circuit
–8–
REV. D