AD608ARZ Datasheet, PDF (9/16 Pages) Analog Devices – Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem

THEORY OF OPERATION
The AD608 consists of a mixer followed by a logarithmic IF
strip with RSSI and hard-limited outputs (see Figure 22).
MIXER
The mixer is a doubly balanced, modified gilbert-cell mixer. Its
maximum input level for linear operation is either ±56.2 mV,
regardless of the impedance across the mixer inputs, or −15 dBm
for a 50 Ω input termination. The input impedance of the mixer
can be modeled as a simple parallel RC network; the resistance
and capacitance values vs. frequency are listed in Table 5. The
bandwidth from the RF input to the IF output at the MXOP pin
is −1 dB at 30 MHz and then rapidly decreases as frequency
increases (see Figure 4).
AD608
MIXER GAIN
The conversion gain of the mixer is the product of its trans-
conductance and the impedance seen at Pin MXOP. For a 330 Ω
parallel-terminated filter at 10.7 MHz, the load impedance is
165 Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV (or
±891 mV) centered on the midpoint of the supply voltage. For
other load impedances, the expression for the gain in decibels is
GdB = 20 log10(0.0961 RL)
where:
GdB is the gain in decibels.
RL is the load impedance at Pin MXOP.
The gain of the mixer can be increased or decreased by changing
RL. The limitations on the gain are the ±6 mA maximum output
current at MXOP and the maximum allowable voltage swing at
Pin MXOP, which is ±1.0 V for a 3 V supply or 5 V supply.
24dB MIXER GAIN
3dB NOMINAL
INSERTION LOSS
110dB LIMITER GAIN
90dB RSSI
RFHI 5
RF INPUT
–95dBm TO
–15dBm¹
RFLO 6
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
MIXER
LO
PREAMP
MXOP
7
BPF
DRIVER
VMID
8
MIDSUPPLY
IF BIAS
BIAS
IF INPUT
–75dBm TO
+15dBm²
10.7MHz
BAND-PASS
FILTER
IFHI
9
330Ω
100nF
330Ω
10nF
+
100Ω
10
IFLO
18nF
13
FDBK
VPS1 COM1 LOHI COM2 PRUP
1
2
3
4
16
7 FULL-WAVE
RECTIFIER CELLS
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
2MHz
LPF
RSSI
RSSI OUTPUT
11 _20mV/dB
0.2V TO 1.8V
COM3 12
VPS2 _{14 2.7V TO 5.5V}
LMOP
15 LIMITER
OUTPUT
FINAL
400mV p-p
LIMITER
AD608
±50µA
2.7V TO
5.5V
LO INPUT
–16dBm
CMOS LOGIC
INPUT
1_{–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.}
2_{39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.}
Figure 22. Functional Block Diagram
Table 5. Mixer Input Impedance vs. Frequency
Frequency (MHz)
Resistance (Ω)
45
2800
70
2600
100
1900
200
1200
300
760
400
520
500
330
Capacitance (pF)
3.1
3.1
3.0
3.1
3.2
3.4
3.6
Rev. C | Page 9 of 16