AD5380_15 Datasheet, PDF (9/40 Pages) Analog Devices – 40-Channel, 3 V/5 V, Single-Supply, 14-Bit, denseDAC

Data Sheet
AD5380
TIMING CHARACTERISTICS
SERIAL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX,
unless otherwise noted.
Table 4.
Parameter^{1, 2, 3}
t1
t2
t3
t4
t5 ⁴
t64
t7
t7A
t8
t9
t104
t11
t124
t13
t14
t15
t16
t17
t18
t19
t20 ⁵
t215
t225
t23
Limit at TMIN, TMAX
33
13
13
13
13
33
10
140
5
4.5
36
670
20
20
100/2000
0
100/2000
3
20
40
30
5
8
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min/max
ns min
ns min/max
µs typ
ns min
µs max
ns max
ns min
ns min
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24^th SCLK falling edge to SYNC falling edge
Minimum SYNC low time
Minimum SYNC high time
Minimum SYNC high time in readback mode
Data setup time
Data hold time
24th SCLK falling edge to BUSY falling edge
BUSY pulse width low (single channel update)
24th SCLK falling edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time; boost mode off
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
1 _{Guaranteed by design and characterization, not production tested.}
2 _{All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC), and are timed from a voltage level of 1.2 V.}
3 _{See Figure 2, Figure 3, Figure 4, and Figure 5.}
4 _{Standalone mode only.}
5 _{Daisy-chain mode only.}
200µA
I_OL
TO OUTPUT PIN
C_L
50pF
200µA
I_OH
V_OH (MIN) OR
V_OL (MAX)
Figure 2. Load Circuit for Digital Output Timing
Rev. D | Page 9 of 40