ADF7242 Datasheet, PDF (89/108 Pages) Analog Devices – Low Power IEEE 802.15.4/Proprietary GFSK/FSK Zero-IF 2.4 GHz Transceiver IC

ADF7242
Table 51. 0x100: ext_ctrl
Bit Field Name
R/W Reset Value Description
[7] pa_shutdown_mode R/W 0
PA shutdown mode.
0: fast ramp-down.
1: user defined ramp-down.
[6:5] Reserved
R/W 0
Reserved, set to default.
4
rxen_en
R/W 0
1: RXEN_GP6 is set high while in the RX state; otherwise, it is low.
0: RXEN_GP6 is under user control (refer to Register gp_out); refer to
Register gp_cfg for restrictions
3
txen_en
R/W 0
1: TXEN_GP5 is set high while in the TX state; otherwise, it is low.
0: TXEN_GP5 is under user control (refer to Register gp_out); refer to
Register gp_cfg for restrictions.
2
extpa_auto_en
R/W 0
1: RC enables external PA controller while in the TX state.
0: Register pd_aux, Bit extpa_bias_en (0x31E[4]) is under user control.
[1:0] Reserved
R/W 0
Reserved, set to default.
Table 52. 0x102: fsk_preamble
Bit Field Name
R/W
[7:0] Nbtx_preamble_byte R/W
Reset Value
8
Description
Set the number of preamble bytes that is appended at the beginning of a TX
GFSK/FSK frame.
Note that the packet manager automatically transmits another n bytes of
preamble, with n set by MCR Register 0x3F3. Depending on the SWD used, there
may also be additional preamble bits contained in Register 0x10C to Register
0x10E. Refer to the Transmitter in GFSK/FSK Mode section for details.
Table 53. 0x105: cca1
Bit Field Name R/W
[7:0] cca_thres R/W
Reset Value
171
Description
RSSI threshold for CCA. Signed twos complement notation (in dBm). When CCA is completed:
Status Word CCA_RESULT = 1 if Register rrb, Bit rssi_readback (0x30C[7:0]) < cca_thres
Status Word CCA_RESULT = 0 if Register rrb, Bit rssi_readback (0x30C[7:0]) ≥ cca_thres
Table 54. 0x106: cca2
Bit
Field Name
[7:3] Reserved
2
continuous_cca
1
rx_auto_cca
0
Reserved
R/W Reset Value Description
R/W 0
Reserved, set to default.
R/W 0
0: continuous CCA off.
1: generate a CCA interrupt every 128 μs.
R/W 0
0: automatic CCA off.
1: generate a CCA interrupt 128 μs after entering the RX state.
R/W 0
Reserved, set to default.
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