AD6676 Datasheet, PDF (86/90 Pages) Analog Devices – Wideband IF Receiver Subsystem

AD6676
PHY Control 3 Register
Address: 0x1EF, Reset: 0x00, Name: PRE-EMPHASIS
Table 117. Bit Descriptions for PRE-EMPHASIS
Bits
Bit Name
Description
7
SER_EMP_PS1
Toggle Polarity of Lane 1 Emphasis.
[6:4]
SER_EMP_IDAC1
Lane 1 IDAC Setting.
00: 0 mV emphasis differential p-p.
01: 160 mV emphasis differential p-p.
10: 80 mV emphasis differential p-p.
11: 40 mV emphasis differential p-p.
3
SER_EMP_PS0
Toggle polarity of Lane 0 emphasis.
[2:0]
SER_EMP_IDAC0
Lane 0 IDAC Setting.
00: 0 mV emphasis differential p-p.
01: 160 mV emphasis differential p-p.
10: 80 mV emphasis differential p-p.
11: 40 mV emphasis differential p-p.
ADC Standby 0 Register
Address: 0x250, Reset: 0xFF, Name: STBY_DAC
Table 118. Bit Descriptions for STBY_DAC
Bits
Bit Name
Description
[7:0]
STBY_DAC
Setting register to 0x95 results in faster standby ADC recovery time.
CLKSYN Enable Register
Address: 0x2A0, Reset: 0x00, Name: CLKSYN_ENABLE
Table 119. Bit Descriptions for CLKSYN_ENALBE
Bits
Bit Name
Description
7
EN_EXTCK
EXTCK Enable.
6
EN_ADC_CK
ADC CK Enable.
5
EN_SYNTH
Synthesizer Enable.
4
EN_VCO_PTAT
VCO PTAT Enable.
3
EN_VCO_ALC
VCO ALC Enable.
2
EN_VCO
VCO Enable.
1
EN_OVERIDE_CAL
Override Calibration Enable.
0
EN_OVERIDE
Override Enable.
CLKSYN Integer N LSB Register
Address: 0x2A1, Reset: 0x80, Name: CLKSYN_INT_N_LSB
Table 120. Bit Descriptions for CLKSYN_INT_N_LSB
Bits
Bit Name
Description
[7:0]
INT_N_LSB
Lower LSBs of 11-bit Integer-N Value.
Data Sheet
Reset
0x0
0x0
Access
RW
RW
0x0
RW
0x0
RW
Reset
0xFF
Access
RW
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0x80
Access
RW
Rev. A | Page 86 of 90