ADUC842BSZ62-3 Datasheet, PDF (83/88 Pages) Analog Devices – MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU

ADuC841/ADuC842/ADuC843
Parameter
SPI MASTER MODE TIMING (CPHA = 0)
tSL
SCLOCK Low Pulse Width¹
tSH
SCLOCK High Pulse Width¹
tDAV
Data Output Valid after SCLOCK Edge
tDOSU
Data Output Setup before SCLOCK Edge
tDSU
Data Input Setup Time before SCLOCK Edge
tDHD
Data Input Hold Time after SCLOCK Edge
tDF
Data Output Fall Time
tDR
Data Output Rise Time
tSR
SCLOCK Rise Time
tSF
SCLOCK Fall Time
Min
Typ
476
476
100
100
10
10
10
10
1 _{Characterized under the following conditions:}
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
Max
50
150
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLOCK
(CPOL = 0)
SCLOCK
(CPOL = 1)
MOSI
MISO
t_SH
t_SL
t_DOSU
t_DAV
t_DF
MSB
t_DR
BITS 6–1
t_SR
t_SF
LSB
MSB IN
BITS 6–1
LSB IN
t_DSU t_DHD
Figure 92. SPI Master Mode Timing (CPHA = 0)
Rev. 0 | Page 83 of 88