MDS-1020_15 Datasheet, PDF (8/8 Pages) Analog Devices – 8, 10, 12 BIT VIDEO SPEED CURRENT AND VOLTAGE OUT D/A CONVERTERS

(continued from page 1915)
going inputs on all forms of saturated logic. The TTL or DTL
Each DIA is housed in industry standard size cases, and each has
an internal precision reference. Bipolar operation is achieved
by external pin interconnection. In normal circumstances, no
external components are required for operation into [ow im-
driving logic, and the D/A input circuits for current-switching
D/A's are subject to this same characteristic.
Thus, the time skew of the individual current switches within
the converter is worse when one or more input bits are out of
pedance loads. Designed primarily for PCB mounting, these
D/A's may also be plugged into standard DIL sockets mounted
on 1.8" centers (MDS series 2" centers).
phase with the others. This is true even for ideal inputs in
which the digital inputs arrive simultaneously; if there is time
skew among the bit inputs, of course, the problem becomes
more pronounced.
For ultra-high reliability, this D/A series is optionally avail-
able with burn-in extended beyond the Analog Devices
Note, settling times even better than those specified for the
standard of 96 hours at +2SoC.
MDS series become possible if digital input bit arrivals are
deskewed.
NOTES ON FAST-SETTLING D/A CONVERTERS
Invariably, fast-settling D/A converters use current rather than
These differences among the switches cause a discontinuity or
OBSOLETE voltage switching.
There are inherent advantages to current-switching converters,
since it eliminates an output amplifier. If there is no output
amplifier, there is no slew rate limitation which slows settling.
The absence of an output amplifier also means there are no
overshoot and ringing problems often associated with feed-
back amplifiers.
The settling time of a current-switching D/A converter, then,
is based on:
1. The RC time constant of the converter output.
2. The settling time of the output current change.
If the settling time of the D/A converter under consideration
is determined by the RC time consta~t, the output capacitance
and output impedance become very important.
As a typical example in the Analog Devices' D/A converters,
"glitch" in the output. The true "worst case" glitch always
occurs at the switching point of the Most Significant Bit or the
center point of the output range, because nearly equal and
opposite currents are being switched within the converter.
!n addition, all "0" to all "1" switching overlooks the prac-
tical aspects involved. There are relatively few times when all
of the input bits will be changing from one state to the other
on successive input changes; however, the MSB will switch out
of phase with all other bits each time the analog output of the
converter crosses the midpoint.
In considering the choice of a "fast-settling" D/A converter,
then, the user should look for the following points in the
data sheet:
1. If the settling time spec has all bits changing state identi-
c~ly, it neglects the phenomenon associated with saturated
logic discussed earlier.
output capacitance is SpF, and nominal output impedance
2. Is the settling time specified with an impractically-Iow-
is 16Sn.
impedance load?
For teSt purposes, the output of these D/A converters are
loaded with approximately IS0n . (There is no "trick" or
"gimmick" in loading the output of the converter; it is done
to provide an output voltage of approximately 1.OV to 1.2V.)
= This loading means RC 80 X S X 10-12 = DAns. Since set-
tling time is approximately 7 RC, the overall settling time, if
determined by the RC time constant, would be 2.8ns.
Based on this, it becomes obvious the RC time constant of such
converters outputs is not the limiting factor in establishing set-
tling time. Instead, the settling time of the converters is based
primarily on the settling time of the overall (outpu t) current
change, since the effect of the RC time constant is "swamped."
Expressed in another way, this means settling time for the
MDS series converters is relatively independent of load resis-
tance, unless substantial load capacitance is present. The set-
tling time of the output current, in turn, is based on:
If the RC time constant of the converter output is the major
factor in establishing settling time (because of high output
capacitance and lor resistance), a low impedance load helps
make settling time look better.
A low impedance load means the voltage being dev<:loped at
the output is oftentimes too small to be useful.
A higher-impedance load which can develop a useable output
of 1.OV or more sometimes negates the fast settling time of
the spec sheet.
A test setup for this worst-case measurement is shown in Fig-
ure 1. Two pulse generators are used to generate the required
out-of-phase pulses, and the delays are adjusted for minimum
skew. Figure 2 is an unretouched photo of the oscilloscope
trance of an MDS-81S under test.
1. The settling time of each switch within the converter.
2. The time skew among the digital inputs which cause the
switching action.
Some manufacturers of fast-settling D/A converters spec set-
tling time under the conditions of all digital inputs changing
from "0" to "1 H,or vice versa. At first glance, it would appear
this is the "worst case" condition for measuring settling time,
since maximum current is being switched.
Unfortunately, this method of specifying neglects an important
characteristic of saturated logic. . . the propagation delay for
negative-going inputs is different from the delay fo_Pr _apo_gs_eitiv₈e-_{of 8}
MDS.O.'S
EXT. TRIG
OSCillOSCOPE
HIGH SPEEO
TTllOGICGATES
OR INVERTERS
SUCH AS'.H04
OR 10500 TYPE
Figure 1.
O/A CONVERTERS 1955
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