AD9847AKCPZRL Datasheet, PDF (8/28 Pages) Analog Devices – 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver

AD9847
SYSTEM OVERVIEW
Figures 1a and 1b show the typical system application diagrams
for the AD9847. The CCD output is processed by the AD9847’s
AFE circuitry, which consists of a CDS, PxGA, VGA, black
level clamp, and A/D converter. The digitized pixel information is
sent to the digital image processor chip, where all post-processing
and compression occurs. To operate the CCD, CCD timing param-
eters are programmed into the AD9847 from the image processor
through the 3-wire serial interface. From the system master clock,
CLI, provided by the image processor, the AD9847 generates
the high speed CCD clocks and all internal AFE clocks. All
AD9847 clocks are synchronized with VD and HD.
CCD
V-DRIVER
H1–H4, RG
CCDIN
V1–V4, VSG1–VSG8, SUBCK
DOUT
AD9847
INTEGRATED
AFE + TD
HD, VD
DIGITAL IMAGE
PROCESSING
ASIC
CCD
V-DRIVER
V1–V4, VSG1–VSG8, SUBCK
H1–H4, RG
CCDIN
AD9847
INTEGRATED
AFE + TD
DOUT
CLPOB
CLPDM
PBLK
HBLK
HD, VD
CLI
DIGITAL IMAGE
PROCESSING
ASIC
SERIAL
INTERFACE
Figure 1b. Typical Application (External Mode)
Figure 2 shows the horizontal and vertical counter dimensions for
the AD9847. All internal horizontal clocking is programmed using
these dimensions to specify line and pixel locations.
MAXIMUM FIELD DIMENSIONS
CLI
SERIAL
INTERFACE
Figure 1a. Typical Application (Internal Mode)
Figure 1a shows the AD9847 used in internal mode, in which all
the horizontal pulses (CLPOB, CLPDM, PBLK, and HBLK)
are programmed and generated internally. Figure 1b shows the
AD9847 operating in external mode, in which the horizontal
pulses are supplied externally by the image processor.
The H-drivers for H1–H4 and RG are included in the AD9847,
allowing these clocks to be directly connected to the CCD. The
AD9847 supports H-drive voltage of 5 V.
12-BIT HORIZONTAL = 4096 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
Figure 2. Vertical and Horizontal Counters
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REV. A