AD9821 Datasheet, PDF (8/16 Pages) Analog Devices – Complete 12-Bit 40 MSPS Imaging Signal Processor

AD9821
IMAGER MODE AND AUX MODE TIMING
VIN+
VIN–
DATACLK
OUTPUT
DATA
N
t_ID
N+1
N+2
t_CONV
t_OD
N–10
t_H
N–9
N–8
N+9
N+8
N–1
N
NOTES:
1. VIN+ AND VIN– SIGNALS ARE SAMPLED AT DATACLK RISING EDGES (CAN BE INVERTED USING THE CONTROL REGISTER).
2. INTERNAL SAMPLING DELAY (APERTURE) t_ID IS TYPICALLY 3 ns.
3. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
Figure 5. Imager Mode Timing
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING
EFFECTIVE PIXELS
IMAGER
SIGNAL
CLPOB
PBLK
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
EFFECTIVE DATA
NOTES:
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
Figure 6. Typical Imager Mode Line Clamp Timing
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