AD9628 Datasheet, PDF (8/44 Pages) Analog Devices – 12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter

AD9628
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate¹
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1 Mode (t_CLK)
CLK Pulse Width High (t_CH)
Aperture Delay (t_A)
Aperture Uncertainty (Jitter, t_J)
DATA OUTPUT PARAMETERS
CMOS Mode (DRVDD = 1.8 V)
Data Propagation Delay (t_PD)
DCO Propagation Delay (t_DCO)²
DCO to Data Skew (t_SKEW)
LVDS Mode (DRVDD = 1.8 V)
Data Propagation Delay (t_PD)
DCO Propagation Delay (t_DCO)²
DCO to Data Skew (t_SKEW)
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency) Channel A/Channel B
Wake-Up Time (Power Down)³
Wake-Up Time (Standby)
Out-of-Range Recovery Time
AD9628-105
AD9628-125
Temp Min Typ
Max Min Typ
Max Unit
Full
1000
1000 MHz
Full 20
105 20
125 MSPS
Full 10
105 10
125 MSPS
Full
9.52
8
ns
Full
4.76
4
ns
Full
1.0
1.0
ns
Full
0.07
0.07
ps rms
Full 1.8 2.9
Full 2.0 3.1
Full −1.2 −0.1
4.4 1.8 2.9
4.4 2.0 3.1
+1.0 −1.2 −0.1
4.4 ns
4.4 ns
+1.0 ns
Full
2.4
2.4
ns
Full
2.4
2.4
ns
Full −0.20 +0.03 +0.25 −0.20 +0.03 +0.25 ns
Full
16
16
Cycles
Full
16/16.5
16/16.5
Cycles
Full
350
350
µs
Full
250
250
ns
Full
2
2
Cycles
1 _{Conversion rate is the clock rate after the divider.}
2 _{Additional DCO delay can be added by writing to Bit 0 through Bit 2 in SPI Register 0x17 (see Table 18).}
3 _{Wake-up time is defined as the time required to return to normal operation from power-down mode.}
Rev. 0 | Page 8 of 44