AD8561 Datasheet, PDF (8/11 Pages) Analog Devices – Ultrafast 7 ns Single Supply Comparator

AD8561
INPUT STAGE AND BIAS CURRENTS
The AD8561 uses a PNP differential input stage that enables
the input common-mode range to extend all the way from the
negative supply rail to within 2.2 V of the positive supply rail.
The input common-mode voltage can be found as the average
of the voltage at the two inputs of the device. To ensure the
fastest response time, care should be taken not to allow the
input common-mode voltage to exceed either of these voltages.
The input bias current for the AD8561 is 3 µA. As with any
PNP differential input stage, this bias current will go to zero on
an input that is high and will double on an input that is low.
Care should be taken in choosing resistor values to be con-
nected to the inputs as large resistors could cause significant
voltage drops due to the input bias current.
The input capacitance for the AD8561 is typically 3 pF. This is
measured by inserting a 5 kΩ source resistance to the input and
measuring the change in propagation delay.
USING HYSTERESIS
Hysteresis can easily be added to a comparator through the
addition of positive feedback. Adding hysteresis to a comparator
offers an advantage in noisy environments where it is not desir-
able for the output to toggle between states when the input
signal is near the switching threshold. Figure 17 shows a
method for configuring the AD8561 with hysteresis.
SIGNAL
COMPARATOR
The input signal is connected directly to the noninverting input
of the comparator. The output is fed back to the inverting input
through R1 and R2. The ratio of R1 to R1 + R2 establishes the
width of the hysteresis window with V_REF setting the center of
the window, or the average switching voltage. The Q output will
switch high when the input voltage is greater than V_HI and will
not switch low again until the input voltage is less than V_LO as
given in Equation 1:
( ) ^V HI ^{= V} + ^{–1–V} REF
R1
R1+ R2
+V
REF
V _LO
= V _REF

^1–
R1 
R1+ R2_
(1)
Where V₊ is the positive supply voltage.
The capacitor C_F can also be added to introduce a pole into the
feedback network. This has the effect of increasing the amount
of hysteresis at high frequencies. This can be useful when com-
paring a relatively slow signal in a high frequency noise environ-
1
ment. At frequencies greater than f_P = _{2π CF R2}, the hysteresis
window approaches V_HI = V₊ – 1 V and V_LO = 0 V. At frequen-
cies less than f_P the threshold voltages remain as in Equation 1.
R1
R2
V_REF
C_F
Figure 17. Configuring the AD8561 with Hysteresis
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