AD7708BRUZ Datasheet, PDF (8/44 Pages) Analog Devices – 8-/10-Channel, Low Voltage, Low Power,
- ADCs

AD77018–SPECIFICATIONS1
(AV_DD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV_DD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) =
2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T_MIN to T_MAX unless otherwise noted.)
Parameter
B Grade
Unit
Test Conditions
LOGIC INPUTS (Continued)
SCLK Only (Schmitt-Triggered Input)²
V_T(+)
V_T(–)
V_T(+)–V_T(–)
V_T(+)
V_T(–)
V_T(+)–V_T(–)
XTAL1 Only²
V_INL, Input Low Voltage
V_INH, Input High Voltage
V_INL, Input Low Voltage
V_INH, Input High Voltage
Input Currents
Input Capacitance
1.4/2
0.8/1.4
0.3/0.85
0.95/2
0.4/1.1
0.3/0.85
0.8
3.5
0.4
2.5
± 10
–70
10
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V max
V min
V max
V min
µA max
µA max
pF typ
DV_DD = 5 V
DV_DD = 5 V
DV_DD = 5 V
DV_DD = 3 V
DV_DD = 3 V
DV_DD = 3 V
DV_DD = 5 V
DV_DD = 5 V
DV_DD = 3 V
DV_DD = 3 V
Logic Input = DV_DD
Logic Input = DGND, Typical –40 µA @ 5 V
and –20 µA at 3 V
All Digital Inputs
LOGIC OUTPUTS (Excluding XTAL2)⁵
V_OH, Output High Voltage²
V_OL, Output Low Voltage²
V_OH, Output High Voltage²
V_OL, Output Low Voltage²
Floating State Leakage Current
Floating State Output Capacitance
Data Output Coding
DV_DD – 0.6
0.4
4
0.4
± 10
± 10
Binary
Offset Binary
V min
V max
V min
V max
µA max
pF typ
DV_DD = 3 V, I_SOURCE = 100 µA
DV_DD = 3 V, I_SINK = 100 µA
DV_DD = 5 V, I_SOURCE = 200 µA
DV_DD = 5 V, I_SINK = 1.6 mA
Unipolar Mode
Bipolar Mode
SYSTEM CALIBRATION²
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
1.05 × FS
–1.05 × FS
0.8 × FS
2.1 × FS
V max
V min
V min
V max
START-UP TIME
From Power-On
From Power-Down Mode
300
ms typ
1
ms typ
300
ms typ
Oscillator Powered Down
POWER REQUIREMENTS
Power Supply Voltages
AV_DD–AGND
DV_DD–DGND
DI_DD (Normal Mode)
AI_DD (Normal Mode)
DI_DD (Power-Down Mode)
AI_DD (Power-Down Mode)
Power Supply Rejection (PSR)
Chop Disabled
Chop Enabled
AV_DD and DV_DD can be operated independently of each other.
2.7/3.6
V min/max
AV_DD = 3 V nom
4.75/5.25
V min/max
AV_DD = 5 V nom
2.7/3.6
V min/max
DV_DD = 3 V nom
4.75/5.25
V min
DV_DD = 5 V nom
0.55
mA max
DV_DD = 3 V, 0.43 mA typ
0.65
mA
DV_DD = 5 V, 0.5 mA typ
1.1
mA
AV_DD = 3 V or 5 V, 0.85 mA typ
10
µA max
DV_DD = 3 V, 32.768 kHz Osc. Running
2
µA max
DV_DD = 3 V, Oscillator Powered Down
30
µA max
DV_DD = 5 V, 32.768 kHz Osc. Running
8
µA max
DV_DD = 5 V, Oscillator Powered Down
1
µA max
AV_DD = 3 V or 5 V
Input Range = ± 2.56 V, AIN = 1 V
70
dB min
95 dB typ
100
dB typ
NOTES
1_{Temperature range is –40°C to +85°C.}
2_{Not production tested, guaranteed by design and/or characterization data at release.}
3_{Following a self-calibration this error will be in the order of the noise for the programmed gain and update selected. A system calibration will completely}
remove this error.
4_{Recalibration at any temperature will remove these errors.}
5_{I/O Port Logic Levels are with respect to AVDD and AGND.}
Specifications are subject to change without notice.
–8–
REV. 0