AD7091R-5_17 Datasheet, PDF (8/35 Pages) Analog Devices – 4-Channel, I 2 C, Ultralow Power 12-Bit ADC in 20-Lead LFCSP/TSSOP

Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD7091R-5
AS₀ 1
RESET 2
V_DD 3
REGCAP 4
REF_IN/REF_OUT 5
GND 6
20 V_DRIVE
19 CONVST/GPO₁
AD7091R-5
TOP VIEW
(Not to Scale)
18 SCL
17 SDA
16 AS₁
15 GND
MUX_OUT 7
V_IN0 8
V_IN2 9
ALERT/BUSY/GPO₀ 10
14 ADC_IN
13 V_IN1
12 V_IN3
11 GPO₂
V_DD 1
REGCAP 2
REF_IN/REF_OUT 3
GND 4
MUX_OUT 5
AD7091R-5
TOP VIEW
(Not to Scale)
15 SDA
14 AS₁
13 GND
12 ADCIN
11 V_IN1
Figure 3. Pin Configuration, 20-Lead TSSOP
NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. IT IS RECOMMENDED THAT THE PAD BE
SOLDERED TO GND.
Figure 4. Pin Configuration, 20-Lead LFCSP
Table 5. Pin Function Descriptions
Pin No.
TSSOP
LFCSP Mnemonic
1
19
AS0
2
20
RESET
3
1
VDD
4
2
REGCAP
5
3
REFIN/REFOUT
6, 15
7
8
9
10
4, 13
5
GND
MUXOUT
6
VIN0
7
VIN2
8
ALERT/BUSY/GPO0
11
9
GPO2
12
10
VIN3
13
11
VIN1
14
12
ADCIN
Description
I²C Address Bit 0. Together with AS1, the logic state of these two inputs selects a unique I²C
address for the AD7091R-5. The device address depends on the logic state of these pins.
Reset. Logic input. This pin resets the device when pulled low.
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
Decoupling Capacitor Pin for Voltage Output from the Internal Regulator. Decouple this output
pin separately to GND using a 2.2 µF capacitor.
Voltage Reference Output, 2.5 V. Decouple this pin to GND. The typical recommended
decoupling capacitor value is 2.2 µF. The user can either access the internal 2.5 V reference or
overdrive the internal reference with the voltage applied to this pin. The reference voltage range for
an externally applied reference is 1.0 V to VDD.
Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-5.
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or
buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the
conditioning network to the ADCIN pin.
Analog Input for Channel 0. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input for Channel 2. Single-ended analog input. The analog input range is 0 V to VREF.
This is a multifunction pin determined by the configuration register.
Alert Output Pin (ALERT). When functioning as ALERT, this pin is a logic output indicating that a
conversion result has fallen outside the limit of the register settings.
Busy Output (BUSY). The BUSY pin indicates when a conversion is taking place.
General-Purpose Digital Output 0 (GPO0).
General-Purpose Digital Output 2.
Analog Input for Channel 3. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input for Channel 1. Single-ended analog input. The analog input range is 0 V to VREF.
ADC Input. This pin allows direct access to the ADC. If no external filtering or buffering is
required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the conditioning
network to the MUXOUT pin.
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