AD5530_07 Datasheet, PDF (8/20 Pages) Analog Devices – Serial Input, Voltage Output 12-/14-Bit Digital-to-Analog Converters

AD5530/AD5531
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFAGND 1
REFIN 2
LDAC 3
SDIN 4
SYNC 5
AD5530/
AD5531
TOP VIEW
(Not to Scale)
16 V_DD
15 V_OUT
14 DUTGND
13 V_SS
12 NC
RBEN 6
11 GND
SCLK 7
10 PD
SDO 8
9 CLR
NC = NO CONNECT
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1
REFAGND For bipolar ±10 V output range, this pin should be tied to 0 V.
2
REFIN
This is the voltage reference input for the DAC. Connect to external 5 V reference for specified bipolar ±10 V output.
3
LDAC
Load DAC Logic Input (Active Low). When taken low, the contents of the shift register are transferred to the DAC
register. LDAC can be tied permanently low, enabling the outputs to be updated on the rising edge of SYNC.
4
SDIN
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the falling edge of SCLK.
5
SYNC
Active Low Control Input. Data is clocked into the shift register on the falling edges of SCLK.
6
RBEN
Active Low Readback Enable Function. This function allows the contents of the DAC register to be read. Data
from the DAC register is shifted out on the SDO pin on each rising edge of SCLK.
7
SCLK
Clock Input. Data is clocked into the input register on the falling edge of SCLK.
8
SDO
Serial Data Out. This pin is used to clock out the serial data previously written to the input shift register or can be
used in conjunction with RBEN to read back the data from the DAC register. This is an open drain output; it
should be pulled high with an external pull-up resistor. In standalone mode, SDO should be tied to GND or left
high impedance.
9
CLR
Level Sensitive, Active Low Input. A falling edge of CLR resets VOUT to DUTGND. The contents of the registers
are untouched.
10
PD
This allows the DAC to be put into a power-down state.
11
GND
Ground Reference.
12
NC
Do not connect anything to this pin.
13
VSS
Negative Analog Supply Voltage. −12 V ± 10% or −15 V ± 10%, for specified performance.
14
DUTGND
VOUT is referenced to the voltage applied to this pin.
15
VOUT
DAC Output.
16
VDD
Positive Analog Supply Voltage. 12 V ± 10% or 15 V ± 10%, for specified performance.
Rev. B | Page 8 of 20