AD538 Datasheet, PDF (8/11 Pages) Analog Devices – Real-Time Analog Computational Unit ACU

AD538
TWO-QUADRANT DIVISION
The two-quadrant linear divider circuit illustrated in Figure 13
uses the same basic connections as the one-quadrant version.
However, in this circuit the numerator has been offset in the
positive direction by adding the denominator input voltage to it.
The offsetting scheme changes the divider’s transfer function
from:
V_O
= 10V
 V_Z
 ^VX


to:
( ) _{VO = 10V} ^VZ ^{+ AV}X
V_X
= 10 V

¹
A
+
V_Z
V_X


= 10
A
+
10
V


V_Z
V_X


where
A=
 35 kΩ 
 ^{25 kΩ} 
As long as the magnitude of the denominator input is equal to
or greater than the magnitude of the numerator input, the cir-
cuit will accept bipolar numerator voltages. However, under the
conditions of a 0 V numerator input, the output would incor-
rectly equal +14 V. The offset can be removed by connecting
the +10 V reference through resistors R1 and R2 to the output
section’s summing node I at Pin 9 thus providing a gain of 1.4
at the center of the trimming potentiometer. The pot R2 adjusts
out or corrects this offset, leaving the desired transfer function
of 10 V (V_Z / V_X).
NUMERATOR
OPTIONAL
V_Z
Z OFFSET TRIM
–V_S
AD589
1M⍀
V_OS ADJ
68k⍀
5%
–1.2V
10M⍀
3.9M⍀
35k⍀
I_Z
1
V_Z 25k⍀
2
( ) V_OUT = 10
V_Z
V_X
FOR
V_X Ն V_Z
LOG
RATIO
B₃
DENOMINATOR
V_X
18 A
35k⍀
17 D
16 ^IX
OUTPUT
+10V
4
+2V 5
+15V
6
–15V
7
V_O
8
R2 R1
10k⍀ 12.4k⍀ _I
9
ZERO
ADJUST
100⍀
INTERNAL
VOLTAGE
REFERENCE
OUTPUT
100⍀
15 ^VX
25k⍀ SIGNAL
14 ^GND
PWR
AD538
13 ^GND
IN4148
12 ^C
25k⍀
ANTILOG
LOG
11 ^IY
V_Y
10
25k⍀
LOG RATIO OPERATION
Figure 14 shows the AD538 configured for computing the log of
the ratio of two input voltages (or currents). The output signal
from B is connected to the summing junction of the output ampli-
fier via two series resistors. The 90.9 Ω metal film resistor effec-
tively degrades the temperature coefficient of the ± 3500 ppm/°C
resistor to produce a 1.09 kΩ +3300 ppm/°C equivalent value.
In this configuration, the V_Y input must be tied to some voltage
less than zero (–1.2 V in this case) removing this input from the
transfer function.
The 5 kΩ potentiometer controls the circuit’s scale factor ad-
justment providing a +1 V per decade adjustment. The output
offset potentiometer should be set to provide a zero output with
V_X = V_Z = 1 V. The input V_Z adjustment should be set for an
output of 3 V with V_Z = l mV and V_X = 1 V.
–V_S
68k⍀
5%
AD589
–1.2V
( ) V_O = 1V LOG₁₀
V_Z
V_X
10M⍀ I_Z
1M⍀
1
A
18
OPTIONAL
INPUT V_OS
ADJUSTMENT
90.9⍀
1%
1k⍀
+3500
ppm/؇C
OUTPUT
5k⍀ 2k⍀
1%
SCALE
FACTOR
ADJUST
V_Z 25k⍀
2
LOG
RATIO
D ^48.7⍀
17
B₃
+10V
4
+2V
5
+15V 6
–15V 7
V_O
8
I
9
100⍀
INTERNAL
VOLTAGE
REFERENCE
OUTPUT
16 IX
V_X
100⍀
V_X INPUT
15
25k⍀ _SIGNAL
GND
14
PWR
AD538
13 ^GND
12 ^C
25k⍀
ANTILOG
LOG
I_Y
11
IN4148
10 ^VY
25k⍀
+V_S
10M⍀
10k⍀
–V_S
OPTIONAL
OUTPUT V_OS
ADJUSTMENT
Figure 14. Log Ratio Circuit
The log ratio circuit shown achieves ±0.5% accuracy in the log
domain for input voltages within three decades of input range:
10 mV to 10 V. This error is not defined as a percent of full-
scale output, but as a percent of input. For example, using a
1 V/decade scale factor, a 1% error in the positive direction at
the INPUT of the log ratio amplifier translates into a 4.3 mV
deviation from the ideal OUTPUT (i.e., 1 V × log₁₀ (1.01) =
4.3214 mV). An input error 1% in the negative direction is
slightly different, giving an output deviation of 4.3648 mV.
Figure 13. Two-Quadrant Division with 10 V Scaling
–8–
REV. C