AD1678_15 Datasheet, PDF (8/12 Pages) Analog Devices – 12 BIT 200KSPS SAMPLING ADC

AD1678 PIN DESCRIPTION
Pin No. _Type Name and Function
AGND
7
P
Analog Ground.
AIN
6
Al
Analog Signal Input.
BIPOFF
10
Al
Bipolar Offset. Connect to AGND for + lOV input unipolar mode and straight binary output
(
coding. Connect to REF OUT through SOD resistor for :t5V input bipolar mode and twos
complement binary output coding. See Figures 8 and 9.
CS
4
Dl
Chip Select. Active LOW.
)
DGND
14
P
Digital Ground
DBll-DB4 26-19
DO _{Data Bits 11 through 4. In l2-bit format (see 12/8 pin), these pins provide the upper 8 bits of}
data. In 8-bit format, these pins provide all 12 bits in two bytes (see R/L pin). Active HIGH.
DB3, DB2 18, 17 ^DO Data Bits 3 and 2. In l2-bit format, these pins provide Data Bit 3 and Data Bit 2. Active
DB 1 (R/L) ¹⁶
DBO(HBE) ¹⁵
EOC
27
HIGH. In 8-bit format they are undefined and should be tied to VDD'
DO _{In l2-bit format, Data Bit 1. Active HIGH.}
DO _{In l2-bit format, Data Bit O. Active HIGH.}
DO _{End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the}
conversion is finished. In asynchronous mode, EOC is an open drain output and requires an
external 3kD pull-up resistor. See EOCEN and SYNC pins for information on EOC gating.
OBSOLETE ^EOCEN
1
HBE(DBO) ¹⁵
OE
2
REFJN
9
REFouT
8
R/L(DB!) ¹⁶
SC
3
SYNC
13
Vcc
11
VEE
5
VDD
28
12/8
12
DI
End-Of-Convert Enable. Enables EOC pin. Active LOW.
DI
In 8-bit format, High Byte Enable. If LOW, output contains high byte. If HIGH, output
contains low byte.
DI
Output Enable. The falling edge of OE enables DBll-DBO in l2-bit format and
DBll-DB4 in 8-bit format. Gated with CS. Active LOW.
AI
Reference Input. + 5V input gives lOV full scale range.
AO _{+5V Reference Output. Tied to REF IN through SODresistor for normal operation.}
DI
In 8-bit format, Right/Left justified. Sets alignment of l2-bit result within l6-bit field. Tied to
VDD for right-justified output and tied to DGND for left-justified output.
DI
Start Convert. Active LOW. See SYNC pin for gating.
DI
Sync Control. If tied to VDD (synchronous mode), SC, EOC and EOCEN are gated by CS. If
tied to DGND (asynchronous mode), SC and EOCEN are independent of CS, and EOC is an
open drain output. EOC requires an external 3kD pull-up resistor in asynchronous mode.
P
+ l2V Analog Power.
P
-12V Analog Power.
P
+5V Digital Power.
DI
Twelve/eight bit format. If tied HIGH, sets output format to 12-bit parallel. If tied LOW, sets
(
output format to 8-bit multiplexed.
Type: AI = Analog Input.
AO = Analog Output.
DI = Digital Input (TTL and SV CMOS compatible).
DO = Digital Output (TTL and SV CMOS compatible).
P = Power.
All DO pins are three-state
drivers.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Ceramic DIP Package (D-28A)
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