AD14160 Datasheet, PDF (8/52 Pages) Analog Devices – Quad-SHARC DSP Multiprocessor Family

AD14160/AD14160L
PIN FUNCTION DESCRIPTIONS
AD14160/AD14160L pin definitions are listed below. Inputs
identified as synchronous (S) must meet timing requirements
with respect to CLKIN (or with respect to TCK for TMS,
TDI). Inputs identified as asynchronous (A) can be asserted
asynchronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to V_DD or GND, except
for ADDR_31-0, DATA_47-0, FLAG_2-0, SW, and inputs that have
internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,
TCLKx, RCLKx, LxDAT_3-0, LxCLK, LxACK, TMS and
TDI)—these pins can be left floating. These pins have a logic-
level hold circuit that prevents the input from floating internally.
A = Asynchronous O = Output
(A/D) = Active Drive
G = Ground
P = Power Supply (O/D) = Open Drain
I = Input
S = Synchronous
T = Three-State (when SBTS is asserted, or when the AD14160/
AD14160L is a bus slave)
Pin
ADDR_31-0
DATA_47-0
MS_3-0
RD
WR
PAGE
ADRCLK
SW
ACK
Type
I/O/T
I/O/T
O/T
I/O/T
I/O/T
O/T
O/T
I/O/T
I/O/S
Function
External Bus Address. (Common to all SHARCs) The AD14160/AD14160L outputs addresses for
external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs ad-
dresses for read/writes on the internal memory or IOP registers of slave ADSP-2106xs. The AD14160/
AD14160L inputs addresses when a host processor or multiprocessing bus master is reading or writing
the internal memory or IOP registers of internal ADSP-21060s.
External Bus Data. (Common to all SHARCs) The AD14160/AD14160L inputs and outputs data and
instructions on these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is trans-
ferred over bits 47-16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 47-
8 of the bus. 16-bit short word data is transferred over bits 31-16 of the bus. In PROM boot mode, 8-bit
data is transferred over bits 23-16. Pull-up resistors on unused DATA pins are not necessary.
Memory Select Lines. (Common to all SHARCs) These lines are asserted (low) as chip selects for the
corresponding banks of external memory. Memory bank size must be defined in the individual ADSP-
21060’s system control registers (SYSCON). The MS_3-0 lines are decoded memory address lines that
change at the same time as the other address lines. When no external memory access is occurring the MS_3-0
lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether
or not the condition is true. MS₀ can be used with the PAGE signal to implement a bank of DRAM memory
(Bank 0). In a multiprocessing system, the MS_3-0 lines are output by the bus master.
Memory Read Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14160/
AD14160L reads from external devices or when the internal memory of internal ADSP-2106xs is being
accessed. External devices (including other ADSP-2106xs) must assert RD to read from the AD14160/
AD14160L’s internal memory. In a multiprocessing system, RD is output by the bus master and is input
by all other ADSP-2106xs.
Memory Write Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14160/
AD14160L writes to external devices or when the internal memory of internal ADSP-2106xs is being
accessed. External devices (including other ADSP-2106xs) must assert WR to write to the AD14160/
AD14160L’s internal memory. In a multiprocessing system WR is output by the bus master and is input by all
other ADSP-2106xs.
DRAM Page Boundary. (Common to all SHARCs) The AD14160/AD14160L asserts this pin to signal
that an external DRAM page boundary has been crossed. DRAM page size must be defined in the indi-
vidual ADSP-21060’s memory control register (WAIT). DRAM can only be implemented in external
memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system,
PAGE is output by the bus master.
Clock Output Reference. (Common to all SHARCs) In a multiprocessing system, ADRCLK is output
by the bus master.
Synchronous Write Select. (Common to all SHARCs) This signal is used to interface the AD14160/
AD14160L to synchronous memory devices (including other ADSP-2106xs). The AD14160/AD14160L
asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR
is not later asserted (e.g., in a conditional write instruction). In a multiprocessing system, SW is output
by the bus master and is input by all other ADSP-2106xs to determine if the multiprocessor memory
access is a read or write. SW is asserted at the same time as the address output. A host processor using
synchronous writes must assert this pin when writing to the AD14160/AD14160L.
Memory Acknowledge. (Common to all SHARCs) External devices can deassert ACK (low) to add
wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other pe-
ripherals to hold off completion of an external memory access. The AD14160/AD14160L deasserts ACK,
as an output, to add wait states to a synchronous access of its internal memory. In a multiprocessing
system, a slave ADSP-2106x deasserts the bus master’s ACK input to add wait state(s) to an access of its
internal memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level
it was last driven to.
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REV. A