ADV7183A Datasheet, PDF (75/104 Pages) Analog Devices – Multiformat SDTV Video Decoder

ADV7183A
Table 180. Register 0x09 to 0x0E
Bit
Subaddress Register
Bit Description
7 6 5 4 3 2 1 0 Register Setting
Comments
0x09
Reserved
(Saturation)
Reserved
10000000
0x0A
Brightness
Register
BRI[7:0]. This register controls
the brightness of the video
signal.
00000000
0x00 = 0IRE;
0x7F = 100IRE;
0xFF = –100IRE
0x0B
Hue Register
HUE[7:0]. This register
contains the value for the color _{0 0 0 0 0 0 0 0}
hue adjustment.
Hue range =
–90° to +90°
0x0C
Default Value Y DEF_VAL_EN. Default value
enable.
0 Free Run mode
dependent on
DEF_VAL_AUTO_EN
1 Force SDP Free Run
mode on and output
blue screen
DEF_VAL_AUTO_EN. Default
value.
0
Disable SDP Free Run When lock is lost,
mode
Free Run mode
1
Enable Automatic Free ^{can be enabled}
Run mode (blue
to output stable
screen)
timing, clock,
and a set color.
DEF_Y[5:0]. Default value Y.
This register holds the Y
default value.
001101
Y[7:0] = {DEF_Y[5:0],
0, 0, 0, 0}
Default Y value
output in free-
run mode.
0x0D
Default Value C DEF_C[7:0]. Default value C. Cr
and Cb default values are
defined in this register.
Cr[7:0] = {DEF_C[7:4],
0, 0, 0, 0, 0, 0}
Cb[7:0] = {DEF_C[3:0],
0, 0, 0, 0, 0, 0}
01111100
Default Cb/Cr
value output in
Free Run mode.
Default values
give blue screen
output.
0x0E
ADI Control
DR_STR_S[1:0]. Select the
drive strength of the sync
signals. HS, VS, and F can be
increased or decreased for
EMC or crosstalk reasons.
0 0 Low drive strength
(1×)
0 1 Medium-low (2×)
1 0 Medium-high (3×)
1 1 High drive strength
(4×)
DR_STR_C[1:0]. Select the
strength of the clock signal
output driver. Can be
increased or decreased for
EMC or crosstalk reasons.
00
01
10
Low drive strength
(1×)
Medium-low (2×)
Medium-high (3×)
11
High drive strength
(4×)
Reserved
00
TRI_LLC. Enables the LLC pin
to be three-stated.
0
1
Set as default
LLC pin active
LLC pin drivers three-
stated
See TOD
(Table 177);
TIM_OE
(Table 178).
Reserved
0
Set as default
Rev. A | Page 75 of 104