AD9520-5 Datasheet, PDF (75/80 Pages) Analog Devices – 12 LVPECL/24 CMOS Output Clock Generator

APPLICATIONS INFORMATION
FREQUENCY PLANNING USING THE AD9520
The AD9520 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9520, the following guidelines
should be kept in mind.
The AD9520 has four frequency dividers: the reference (or R)
divider, the feedback (or N) divider, the VCO divider, and the
channel divider. When trying to achieve a particularly difficult
frequency divide ratio requiring a large amount of frequency
division, some of the frequency division can be done by either
the VCO divider or the channel divider, thus allowing a higher
phase detector frequency and more flexibility in choosing the
loop bandwidth.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current and, thus, allows the designer
to fine-tune the PLL loop bandwidth in either direction.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com and is a very accurate tool
for determining the optimal loop filter for a given application.
USING THE AD9520 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock of the AD9520. An ADC can be thought of as a
sampling mixer, and any noise, distortion, or time jitter on the
clock is combined with the desired signal at the analog-to-
digital output. Clock integrity requirements scale with the analog
input frequency and resolution, with higher analog input
frequency applications at ≥14-bit resolution being the most
stringent. The theoretical SNR of an ADC is limited by the ADC
resolution and the jitter on the sampling clock. Considering an
ideal ADC of infinite resolution where the step size and
quantization error can be ignored, the available SNR can be
expressed approximately by
SNR(dB)
=
20
log_{⎜⎜⎝⎛}
1
2πf _At _J
⎟⎟⎠⎞
where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Figure 57 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
AD9520-5
110
1
18
100
SNR = 20log _2πfAtJ
16
90
80
70
t_J
t_J
t_J
=
=
=
100fs
200fs
400fs
14
12
t_{J = 1ps}
60
t_{J = 2ps}
10
50
40
30
10
t_{J = 10ps}
8
6
100
1k
f_A (MHz)
Figure 57. SNR and ENOB vs. Analog Input Frequency
See the AN-756 Application Note and the AN-501 Application
Note at www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sampling clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.
The differential LVPECL outputs of the AD9520 enable clock
solutions that maximize converter SNR performance.
The input requirements of the ADC (differential or single-
ended, logic level termination) should be considered when
selecting the best clocking/converter solution.
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9520 provide the lowest jitter
clock signals available from the AD9520. The LVPECL outputs
(because they are open emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 41 shows the LVPECL output stage.
In most applications, a LVPECL far-end Thevenin termination
(see Figure 58) or Y-termination (see Figure 59) is recommended.
In both cases, VS of the receiving buffer should match VS_DRV. If
it does not match, ac coupling is recommended (see Figure 60).
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
where VS_DRV = 2.5 V, the 50 Ω termination resistor connected to
ground in Figure 59 should be changed to 19 Ω.
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