ADSP-BF549_15 Datasheet, PDF (74/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
HOSTDP A/C Timing-Host Read Cycle
Table 54 and Figure 46 describe the HOSTDP A/C host read
cycle timing requirements.
Table 54. Host Read Cycle Timing Requirements
Parameter
Min
Max
Unit
Timing Requirements
t_SADRDL HOST_ADDR and HOST_CE Setup Before HOST_RD Falling Edge
4
ns
t_HADRDH HOST_ADDR and HOST_CE Hold After HOST_RD Rising Edge
2.5
ns
t_RDWL HOST_RD Pulse Width Low (ACK Mode)
t_DRDYRDL + t_RDYPRD + t_DRDHRDY
ns
HOST_RD Pulse Width Low (INT Mode)
1.5 × t_SCLK + 8.7
ns
t_RDWH HOST_RD Pulse Width High or Time Between HOST_RD Rising Edge and 2 × t_SCLK
ns
HOST_WR Falling Edge
t_DRDHRDY HOST_RD Rising Edge Delay After HOST_ACK Rising Edge (ACK Mode) 0
ns
Switching Characteristics
t_SDATRDY HOST_D15–0 Valid Prior HOST_ACK Rising Edge (ACK Mode)
t_SCLK – 4.0
ns
t_DRDYRDL HOST_ACK Falling Edge After HOST_CE (ACK Mode)
11.25
ns
t_RDYPRD HOST_ACK Low Pulse-Width for Read Access (ACK Mode)
NM¹
ns
t_DDARWH HOST_D15–0 Disable After HOST_RD
8.0
ns
t_ACC
HOST_D15–0 Valid After HOST_RD Falling Edge (INT Mode)
1.5 × t_SCLK
ns
t_HDARWH HOST_D15–0 Hold After HOST_RD Rising Edge
1.0
ns
1 _{NM (Not Measured) — This parameter is based on tSCLK. It is not measured because the number of SCLK cycles for which HOST_ACK remains low depends on the Host}
DMA FIFO status. This is system design dependent.
HOST_ADDR
HOST_CE
HOST_RD
HOST_DATA
HOST_ACK
t_SADRDL
t_RDWL
t_SDATRDY
t_ACC
t_HADRDH
t_RDWH
t_DDARWH
t_HDARWH
t_DRDYRDL
t_RDYPRD
t_DRDHRDY
In Figure 46, HOST_DATA is HOST_D0–D15.
Figure 46. HOSTDP A/C—Host Read Cycle
Rev. E | Page 74 of 102 | March 2014