ADATE318 Datasheet, PDF (74/80 Pages) Analog Devices – 600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs, and On-Chip

ADATE318
DETAILED FUNCTIONAL BLOCK DIAGRAMS
PMU CLAMP LEVELS
SHARED WITH HIGH
SPEED DCL CLAMPS
DAC_VCHx
ADDR 0x06, CHx
DAC_VCLx
ADDR 0x07, CHx
DAC_VIT/VCCMx
ADDR 0x02, CHx
HIGH-Z
(IDEAL CLAMP DIODES)
0
TERM
1
DRV_RCV_MODE
(SEE THE DRIVER LOGIC DIAGRAM)
DAC_VIHx
ADDR 0x01, CHx
DAC_VILx
ADDR 0x03, CHx
DATx
DCL_ENABLE
ADDR 0x19[0]
FORCE_DRV
ADDR 0x19[1]
FORCE_STATE[1]
ADDR 0x19[4]
FORCE_STATE[0]
ADDR 0x19[3]
DRV_VT_HIZ
ADDR 0x19[6]
RCVx
1
0
DRV
DRV_RCV_SW
(SEE THE DRIVER LOGIC DIAGRAM)
DRV_LOW_LEAK
(SEE THE DRIVER LOGIC DIAGRAM)
Figure 127. Driver Block Diagram
0
50Ω
DUTx
DRV_LOW_LEAK
DRV_LOW_LEAK = DCL_ENABLE
DRV_RCV_MODE = DRIVE_VT_HIZ + FORCE_DRV × FORCE_STATE[0]
DRV_RCV_SW = FORCE_DRV × FORCE_STATE[1] + FORCE_DRV × RCVx
DRV_RCV_MODE
(SEE THE DRIVER BLOCK DIAGRAM)
DRV_RCV_SW
(SEE THE DRIVER BLOCK DIAGRAM)
Figure 128. Driver Logic Diagram
Rev. 0 | Page 74 of 80