ADV101 Datasheet, PDF (7/12 Pages) Analog Devices – CMOS 80 MHz, Triple 8-Bit Video DAC

If we, therefore, have a graphics system with a 1024 × 1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-
tor of 0.8, then:
Dot Rate = 1024 × 1024 × 60/0.8
Dot Rate = 78.6 MHz
ADV101
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV101
on the rising edge of CLOCK, as previously described in the
“Digital Inputs” section. It is recommended that the CLOCK
input to the ADV101 be driven by a TTL buffer (e.g., 74F244).
RED, BLUE
mA V
GREEN
mA
V
19.05 0.714 26.67 1.000
WHITE LEVEL
92.5 IRE
1.44 0.054
0
0
9.05 0.340
7.62 0.286
0
0
7.5 IRE
40 IRE
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.
2. V_REF = 1.235V, R_SET = 560Ω, I _SYNC CONNECTED TO IOG.
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 3. RGB Video Output Waveform
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
Table I. Video Output Truth Table
Description
IOG
(mA)¹
IOR, IOB
(mA)
REF
DAC
WHITE SYNC BLANK Input Data
WHITE LEVEL
WHITE LEVEL
VIDEO
VIDEO to BLANK
BLACK LEVEL
BLACK to BLANK
BLANK LEVEL
SYNC LEVEL
26.67
26.67
video + 9.05
video + 1.44
9.05
1.44
7.62
0
19.05
1
19.05
0
video + 1.44 0
video + 1.44 0
1.44
0
1.44
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
0
1
1
0
0
0
xxH
FFH
data
data
00H
00H
xxH
xxH
NOTE
1_{Typical with full-scale IOG = 26.67 mA. VREF = 1.235 V, RSET = 560 Ω, ISYNC connected to IOG.}
Video Synchronization and Control
The ADV101 has a single composite video sync (SYNC) input
control. Many graphics processors and CRT controllers have
the ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite SYNC.
In a graphics system which does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry will enable the generation of a composite SYNC signal.
The I_SYNC current output is typically connected directly to the
IOG output, thus encoding video synchronization information
onto the green video channel. If it is not required to encode sync
information onto the ADV101, the SYNC input should be tied
to logic low and I_SYNC should be connected to analog GND.
Reference Input
An external 1.23 V voltage reference is required to drive the
ADV101. The AD589 from Analog Devices is an ideal choice of
reference. It is a two-terminal, low cost, temperature compen-
sated bandgap voltage reference which provides a fixed 1.23 V
output voltage for input currents between 50 µA and 5 mA. Fig-
ure 4 shows a typical reference circuit connection diagram. The
voltage reference gets its current drive from the ADV101’s V_AA
through an external 1 kΩ resistor to the V_REF pin. A 0.1 µF ce-
ramic capacitor is required between the COMP and V_AA. This is
necessary so as to provide compensation for the internal refer-
ence amplifier.
REV. B
–7–