ADT7316 Datasheet, PDF (7/32 Pages) Analog Devices – SPI/I2C Compatible, 10-Bit Digital Temperature Sensor and Quad Voltage Output 12/10/8-Bit DAC

PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
ADT7316/7317/7318 PIN FUNCTION DESCRIPTION
Pin Mnemonic
Description
1
V_OUTB
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
2
V_OUTA
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
3
V_REFAB
Reference Input Pin for DACs A and B.It may be configured as a buffered or unbuffered input
to each or both of the DACs A and B. It has an input range from 0.25 V to V_DD in unbuffered
mode and from 1 V to V_DD in buffered mode.
4
CS
SPI Active low control Input. This is the frame synchronization signal for the input data.
When CS goes low, it enables the input register and data is transferred in and out on the ris-
ing edges of the following serial clocks. This pin must be kept high for I²C mode of operation.
CS is also used as a control pin when selecting the serial interface type after power-up.
5
GND
Ground Reference Point for All Circuitry on the part. Analog and Digital Ground.
6
V_DD
Positive Supply Voltage, +2.7 V to +5.5 V.The supply should be decoupled to ground.
7
D+
Positive connection to external temperature sensor
8
D-
Negative connection to external temperature sensor
9
LDAC
Active low control input that transfers the contents of the input registers to their respective
DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input
registers have new data. This allows simultaneous update of all DAC outputs. Bit C3 of Con-
trol Configuration 3 register enables LDAC pin. Default is with LDAC pin controlling the
loading of DAC registers.
10 INTERRUPT Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active
high interrupt when temperature, V_DD and AIN limits are exceeded. Default is active low.
11 DOUT/ADD SPI Serial Data Output. Logic Output. Data is clocked out of any register at this pin. Data is
clocked out at the falling edge of SCLK.
ADD, I²C serial bus address selection pin. Logic input. During the first valid I²C bus commu-
nication this pin is checked to determine the serial bus address assigned to the ADT7316/17/
18. Any subsequent changes on this pin will have no affect on the I²C serial bus address. A low
on this pin gives the address 1001 000, leaving it floating gives the address 1001 010 and set-
ting it high gives the address 1001 011.
12 SDA/DIN SDA - I²C Serial Data Input. I²C serial data to be loaded into the parts registers is provided
on this input.
DIN - SPI Serial Data Input. Serial data to be loaded into the parts registers is provided on
this input. Data is clocked into a register on the rising edge of SCLK.
13 SCL/SCLK Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock
data out of any register of the ADT7316/7317/7318 and also to clock data into any register
that can be written to.
14
V_REFCD
Reference Input Pin for DACs C and D.It may be configured as a buffered or unbuffered input
to each or both of the DACs C and D. It has an input range from 0.25 V to V_DD in unbuffered
mode and from 1 V to V_DD in buffered mode.
15
V_OUTD
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
16
V_OUTC
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
REV. PrN
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