ADSP-BF522 Datasheet, PDF (7/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
controller to prioritize and control all system events. Conceptu-
ally, interrupts from the peripherals enter into the SIC and are
then routed directly into the general-purpose interrupts of the
CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the processor. Table 2
describes the inputs to the CEC, identifies their names in the
event vector table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the interrupt assignment
registers (SIC_IARx). Table 3 describes the inputs into the SIC
and the default mappings into the CEC.
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
Emulation/Test Control
RESET
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General-Purpose Interrupt 7
General-Purpose Interrupt 8
General-Purpose Interrupt 9
General-Purpose Interrupt 10
General-Purpose Interrupt 11
General-Purpose Interrupt 12
General-Purpose Interrupt 13
General-Purpose Interrupt 14
General-Purpose Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Event
PLL Wakeup Interrupt
DMA Error 0 (generic)
DMAR0 Block Interrupt
DMAR1 Block Interrupt
DMAR0 Overflow Error
DMAR1 Overflow Error
PPI Error
MAC Status
SPORT0 Status
SPORT1 Status
Reserved
Reserved
UART0 Status
UART1 Status
RTC
DMA Channel 0 (PPI/NFC)
DMA Channel 3 (SPORT0 RX)
DMA Channel 4 (SPORT0 TX)
DMA Channel 5 (SPORT1 RX)
DMA Channel 6 (SPORT1 TX)
TWI
DMA Channel 7 (SPI)
DMA Channel 8 (UART0 RX)
DMA Channel 9 (UART0 TX)
DMA Channel 10 (UART1 RX)
DMA Channel 11 (UART1 TX)
General Purpose
Default
Interrupt (at RESET) Peripheral Interrupt ID ^{Core Interrupt ID} SIC Registers
IVG7
0
0
IAR0 IMASK0, ISR0, IWR0
IVG7
1
0
IAR0 IMASK0, ISR0, IWR0
IVG7
2
0
IAR0 IMASK0, ISR0, IWR0
IVG7
3
0
IAR0 IMASK0, ISR0, IWR0
IVG7
4
0
IAR0 IMASK0, ISR0, IWR0
IVG7
5
0
IAR0 IMASK0, ISR0, IWR0
IVG7
6
0
IAR0 IMASK0, ISR0, IWR0
IVG7
7
0
IAR0 IMASK0, ISR0, IWR0
IVG7
8
0
IAR1 IMASK0, ISR0, IWR0
IVG7
9
0
IAR1 IMASK0, ISR0, IWR0
IVG7
10
0
IAR1 IMASK0, ISR0, IWR0
IVG7
11
0
IAR1 IMASK0, ISR0, IWR0
IVG7
12
0
IAR1 IMASK0, ISR0, IWR0
IVG7
13
0
IAR1 IMASK0, ISR0, IWR0
IVG8
14
1
IAR1 IMASK0, ISR0, IWR0
IVG8
15
1
IAR1 IMASK0, ISR0, IWR0
IVG9
16
2
IAR2 IMASK0, ISR0, IWR0
IVG9
17
2
IAR2 IMASK0, ISR0, IWR0
IVG9
18
2
IAR2 IMASK0, ISR0, IWR0
IVG9
19
2
IAR2 IMASK0, ISR0, IWR0
IVG10
20
3
IAR2 IMASK0, ISR0, IWR0
IVG10
21
3
IAR2 IMASK0, ISR0, IWR0
IVG10
22
3
IAR2 IMASK0, ISR0, IWR0
IVG10
23
3
IAR2 IMASK0, ISR0, IWR0
IVG10
24
3
IAR3 IMASK0, ISR0, IWR0
IVG10
25
3
IAR3 IMASK0, ISR0, IWR0
Rev. D | Page 7 of 88 | July 2013