ADSP-2189M Datasheet, PDF (7/32 Pages) Analog Devices – DSP Microcomputer

ADSP-2189M
Table II. ADSP-2189M Modes of Operation
MODE D MODE C MODE B MODE A Booting Method
X
0
0
0
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Full Memory Mode.¹
X
0
1
0
No automatic boot operations occur. Program execution starts at external
memory location 0. Chip is configured in Full Memory Mode. BDMA can
still be used but the processor does not automatically use or wait for these
operations.
0
1
0
0
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode. IACK has active pull-down.
(REQUIRES ADDITIONAL HARDWARE).
0
1
0
1
IDMA feature is used to load any internal memory as desired. Program ex-
ecution is held off until internal program memory location 0 is written to.
Chip is configured in Host Mode. IACK has active pull-down.¹
1
1
0
0
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode; IACK requires external pull-
down. (REQUIRES ADDITIONAL HARDWARE).
1
1
0
1
IDMA feature is used to load any internal memory as desired. Program ex-
ecution is held off until internal program memory location 0 is written to.
Chip is configured in Host Mode. IACK requires external pull-down.¹
NOTE
1_{Considered as standard operating settings. Using these configurations allows for easier design and better memory management.}
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
Power Supplies
The ADSP-2189M has separate power supply connections for
the internal (V_DDINT) and external (V_DDEXT) power supplies.
The internal supply must meet the 2.5 V requirement. The
external supply can be connected to either a 2.5 V or 3.3 V
supply. All external supply pins must be connected to the same
supply. All input and I/O pins can tolerate input voltages up
to 3.6 V regardless of the external supply voltage. This fea-
ture provides maximum flexibility in mixing 2.5 V and 3.3 V
components.
MODES OF OPERATION
Setting Memory Mode
Memory Mode selection for the ADSP-2189M is made during
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Passive Configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
10 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor’s
output driver. For minimum power consumption during power-
down, reconfigure PF2 to be an input, as the pull-up or pull-
down will hold the pin in a known state and will not switch.
Active Configuration involves the use of a three-statable ex-
ternal driver connected to the Mode C pin. A driver’s output
enable should be connected to the DSP’s RESET signal such
that it only drives the PF2 pin when RESET is active (low).
When RESET is deasserted, the driver should three-state, thus
allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level and will not oscillate should the three-state driver’s level
hover around the logic switching point.
IACK Configuration
Mode D = 0 and in host mode: IACK is an active, driven signal
and cannot be wire OR-ed.
REV. A
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