AD9911 Datasheet, PDF (7/44 Pages) Analog Devices – 500 MSPS Direct Digital Synthesizer with 10-Bit DAC

Parameter
Min
I/O PORT TIMING CHARACTERISTICS
Maximum Frequency Clock (SCLK)
Minimum SCLK Pulse Width Low (tPWL)
1.6
Minimum SCLK Pulse Width High (tPWH)
2.2
Minimum Data Set-Up Time (tDS)
2.2
Minimum Data Hold Time
0
Minimum CSB Set-Up Time (tPRE)
1.0
Minimum Data Valid Time for Read Operation 12
MISCELLANEOUS TIMING CHARACTERISTICS
Master_Reset Minimum Pulse Width
1
I/O_Update Minimum Pulse Width
1
Minimum Set-Up Time (I/O_Update to
4.8
SYNC_CLK)
Minimum Hold Time (I/O_Update to
0
SYNC_CLK)
Minimum Set-Up Time (Profile Inputs to
5.4
SYNC_CLK)
Minimum Hold Time (Profile Inputs to
0
SYNC_CLK)
Minimum Set-Up Time (SDIO Inputs to
2.5
SYNC_CLK)
Minimum Hold Time (SDIO Inputs to
0
SYNC_CLK)
Propagation Delay Between REF_CLK and 2.25
SYNC_CLK
CMOS LOGIC INPUT
VIH
2.0
VIL
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
VOH
2.7
VOL
POWER SUPPLY
Total Power Dissipation—Single-Tone Mode
Total Power Dissipation—With Sweep
Accumulator
Total Power Dissipation—3 Spur
Reduction/Multitone Channels Active
Total Power Dissipation—Test-Tone
Modulation
Total Power Dissipation—Full Power Down
IAVDD—Single-Tone Mode
IAVDD— Sweep Accumulator, REF_CLK
Multiplier, and 10-Bit Output Scalar Enabled
IDVDD—Single-Tone Mode
IDVDD—Sweep Accumulator, REF_CLK
Multiplier, and 10-Bit Output Scalar Enabled
IDVDD_I/O
IDVDD_I/O
IAVDD Power-Down Mode
IDVDD Power-Down Mode
Typ Max
200
3.5 5.5
0.8
3
12
−12
2
0.4
241
241
351
264
1.8
73
73
50
50
40
30
0.7
1.1
AD9911
Unit
Test Conditions/Comments
MHz
ns
ns
ns
ns
ns
ns
Minimum pulse width = 1 sync clock period
Minimum pulse width = 1 sync clock period
ns
Rising edge to rising edge
ns
Rising edge to rising edge
ns
ns
ns
ns
ns
V
V
μA
μA
pF
V
V
mW
Dominated by supply variation
mW
Dominated by supply variation
mW
Dominated by supply variation
mW
Dominated by supply variation
mW
mA
mA
mA
mA
mA
IDVDD = read
mA
IDVDD = write
mA
mA
Rev. 0 | Page 7 of 44