AD9869_15 Datasheet, PDF (7/36 Pages) Analog Devices – Broadband Modem Mixed-Signal Front End

AD9869
DIGITAL SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, RSET = 2 kΩ, unless otherwise noted.
Table 4.
Parameter
CMOS LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
Input Capacitance
CMOS LOGIC OUTPUTS (CLOAD = 5 pF)
High Level Output Voltage (IOH = 1 mA)
Low Level Output Voltage (IOH = 1 mA)
Output Rise/Fall Time
High Strength Mode and CLOAD = 15 pF
Low Strength Mode and CLOAD = 15 pF
High Strength Mode and CLOAD = 5 pF
Low Strength Mode and CLOAD = 5 pF
RESET
Minimum Low Pulse Width (Relative to fADC)
1 _{See the Explanation of Test Levels section.}
Temp Test Level¹ Min
Full
VI
Full
VI
DRVDD − 0.7
Full
VI
Full
VI
Full
VI
DRVDD − 0.7
Full
VI
Full
VI
Full
VI
Full
VI
1
Typ
Max Unit
V
0.4 V
12
μA
3
pF
V
0.4 V
1.5/2.3
ns
1.9/2.7
ns
0.7/0.7
ns
1.0/1.0
ns
Clock cycles
SERIAL PORT TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 5.
Parameter
WRITE OPERATION (See Figure 5)
SCLK Clock Rate (fSCLK)
SCLK Clock High (tHI)
SCLK Clock Low (tLOW)
SDIO to SCLK Setup Time (tDS)
SCLK to SDIO Hold Time (tDH)
SEN to SCLK Setup Time (tS)
SCLK to SEN Hold Time (tH)
READ OPERATION (See Figure 6 and Figure 7)
SCLK Clock Rate (fSCLK)
SCLK Clock High (tHI)
SCLK Clock Low (tLOW)
SDIO to SCLK Setup Time (tDS)
SCLK to SDIO Hold Time (tDH)
SCLK to SDIO (or SDO) Data Valid Time (tDV)
SEN to SDIO Output Valid to High-Z (tEZ)
1 _{See the Explanation of Test Levels section.}
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level¹
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min Typ Max Unit
32
MHz
14
ns
14
ns
14
ns
0
ns
14
ns
0
ns
14
14
14
0
2
32
MHz
ns
ns
ns
ns
14
ns
ns
Rev. A | Page 7 of 36