AD9862_15 Datasheet, PDF (7/32 Pages) Analog Devices – Mixed-Signal Front-End Processor for Broadband Communications

AD9860/AD9862
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
Receive Pins
68/70–79
80/82–91
92
D0A to
D9A/D11A
D0B to
D9B/D11B
RxSYNC
98, 99, AVDD
104, 105,
117, 118,
123, 124,
100, 103, AGND
106, 109,
110, 112,
113, 116,
119, 122,
101
REFT_B
102
REFB_B
107
VIN+B
108
VIN–B
111
VREF
114
VIN–A
115
VIN+A
120
REFB_A
121
REFT_A
10-/12-Bit ADC Output of
Receive Channel A
10-/12-Bit ADC Output of
Receive Channel B
Synchronization Clock for
Channel A and Channel B Rx Paths
Analog Supply Pins
Analog Ground Pins
Top Reference Decoupling for
Channel B ADC
Bottom Reference Decoupling
for Channel B ADC
Receive Channel B Differential (+) Input
Receive Channel B Differential (؊) Input
Internal ADC Voltage Reference
Receive Channel A Differential (؊) Input
Receive Channel A Differential (+) Input
Bottom Reference Decoupling for
Channel A ADC
Top Reference Decoupling for
Channel A ADC
Transmit Pins
18, 20 AVDD
Analog Supply Pins
23, 32
19, 24, AGND
27, 28, 31
Analog Ground Pins
21
REFIO
Reference Output, 1.2 V Nominal
22
FSADJ
Full-Scale Current Adjust
25
IOUT–A Transmit Channel A DAC
Differential (؊) Output
26
IOUT+A Transmit Channel A DAC
Differential (+) Output
29
IOUT+B Transmit Channel B DAC
Differential (+) Output
30
IOUT–B Transmit Channel B DAC
Differential (؊) Output
37–48/50 Tx11/Tx13 12-/14-Bit Transmit DAC Data
to Tx0
(Interleaved Data when Required)
51
TxSYNC Synchronization Input for Transmitter
62
MODE/ Configures Default Timing Mode,
TxBLANK* Controls Tx Digital Power Down
*The logic level of the Mode/TxBLANK pin at power up defines the default timing
mode; a logic low configures Normal Operation, logic high configures Alternate
Operation Mode.
Pin No. Mnemonic
Function
Clock Pins
10
11, 16
12
13
14
15
17
64
DLL_Lock
AGND
NC
AVDD
OSC1
OSC2
CLKSEL
CLKOUT2
65
CLKOUT1
DLL Lock Indicator Pin
DLL Analog Ground Pins
No Connect
DLL Analog Supply Pin
Single Ended Input Clock
(or Crystal Oscillator Input)
Crystal Oscillator Input
Controls CLKOUT1 Rate
Clock Output Generated from Input
Clock (DLL Multiplier Setting
and CLKOUT2 Divide Factor)
Clock Output Generated from
Input Clock (1Ï« if CLKSEL = 1
or /2 if CLKSEL = 0)
Various Pins
1
AUX_ADC_A1 Auxiliary ADC A Input 1
3, 4, 13 AVDD
Analog Power Pins
2, 9
AGND
Analog Ground Pins
5
SIGDELT
Digital Output from
Programmable Sigma-Delta
6
AUX_DAC_A Auxiliary DAC A Output
7
AUX_DAC_B Auxiliary DAC B Output
8
AUX_DAC_C Auxiliary DAC C Output
33, 36, 53, DVDD
59, 61, 66,
93
Digital Power Supply Pin
34, 35, 52, DGND
58, 60, 67,
94
Digital Ground Pin
54
SCLK
Serial Bus Clock Input
55
SDO
Serial Bus Data Bit
56
SDIO
Serial Bus Data Bit
57
SEN
Serial Bus Enable
63
RESETB
Reset (SPI Registers and Logic)
95
AUX_SPI_do Optional Auxiliary ADC Serial Bus
Data Out Bit
96
AUX_SPI_clk Optional Auxiliary ADC Serial Bus
Data Out Latch Clock
97
AUX_SPI_csb Optional Auxiliary ADC Serial Bus
Chip Select Bit
128
AUX_ADC_A2 Auxiliary ADC A Input 2
126
AUX_ADC_B1 Auxiliary ADC B Input 1
125
AUX_ADC_B2 Auxiliary ADC B Input 2
127
AUX_ADC_REF Auxiliary ADC Reference
REV. 0
–7–