AD9852_15 Datasheet, PDF (7/52 Pages) Analog Devices – CMOS 300 MSPS Complete DDS

AD9852
Parameter
PARALLEL I/O TIMING CHARACTERISTICS
tASU (Address Setup Time to WR Signal Active)
tADHW (Address Hold Time to WR Signal Inactive)
tDSU (Data Setup Time to WR Signal Inactive)
tDHD (Data Hold Time to WR Signal Inactive)
tWRLOW (WR Signal Minimum Low Time)
tWRHIGH (WR Signal Minimum High Time)
tWR (Minimum WR Time)
tADV (Address to Data Valid Time)
tADHR (Address Hold Time to RD Signal Inactive)
tRDLOV (RD Low to Output Valid)
tRDHOZ (RD High to Data Three-State)
SERIAL I/O TIMING CHARACTERISTICS
tPRE (CS Setup Time)
tSCLK (Period of Serial Data Clock)
tDSU (Serial Data Setup Time)
tSCLKPWH (Serial Data Clock Pulse Width High)
tSCLKPWL (Serial Data Clock Pulse Width Low)
tDHLD (Serial Data Hold Time)
tDV (Data Valid Time)
CMOS LOGIC INPUTS ⁹
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
POWER SUPPLY¹⁰
VS Current¹¹
VS Current¹²
VS Current¹³
PDISS ¹¹
PDISS ¹²
PDISS ¹³
PDISS Power-Down Mode
Test
AD9852ASVZ
AD9852ASTZ
Temp Level Min Typ Max Min Typ Max Unit
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full V
Full IV
Full IV
Full IV
8.0 7.5
8.0 7.5
ns
0
0
ns
3.0 1.6
3.0 1.6
ns
0
0
ns
2.5 1.8
2.5 1.8
ns
7
7
ns
10.5
10.5
ns
15
15 15
15 ns
5
5
ns
15
15 ns
10
10 ns
Full IV
30
30
ns
Full IV
100
100
ns
Full IV
30
30
ns
Full IV
40
40
ns
Full IV
40
40
ns
Full IV
0
0
ns
Full V
30
30
ns
25°C I
25°C I
25°C IV
25°C IV
25°C V
2.2
3
2.2
0.8
±5
±5
3
V
0.8 V
± 12 μA
± 12 μA
pF
25°C I
25°C I
25°C I
25°C I
25°C I
25°C I
25°C I
815 922
640 725
585 660
2.70 3.20
2.12 2.52
1.93 2.29
1
50
585 660 mA
465 520 mA
425 475 mA
1.93 2.39 W
1.53 1.81 W
1.40 1.65 W
1
50 mW
1 _{The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine waves centered at one-half the applied VDD or a 3 V TTL-level pulse input.}
2 _{An internal 400 mV p-p differential voltage swing equates to 200 mV p-p applied to both REFCLK input pins.}
3 _{Pipeline delays of each individual block are fixed; however, if the first eight MSBs of a tuning word are all 0s, the delay appears longer. This is due to insufficient phase}
accumulation per a system clock period to produce enough LSB amplitude to the D/A converter.
4 _{If a feature such as inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amount.}
5 _{The I/O UD CLK transfers data from the I/O port buffers to the programming registers. This transfer is measured in system clocks.}
6 _{A change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.}
7 _{Represents the comparator’s inherent cycle-to-cycle jitter contribution. The input signal is a 1 V, 40 MHz square wave, and the measurement device is a Wavecrest DTS-2075.}
8 _{Comparator input originates from analog output section via external 7-pole elliptic low-pass filter. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 Ω.}
9 _{Avoid overdriving digital inputs. (Refer to equivalent circuits in Figure 3.)}
10 _{If all device functions are enabled, it is not recommended to simultaneously operate the device at the maximum ambient temperature of 85°C and at the maximum}
internal clock frequency. This configuration may result in violating the maximum die junction temperature of 150°C. Refer to the Power Dissipation and Thermal
Considerations section for derating and thermal management information.
11 _{All functions engaged.}
12 _{All functions except inverse sinc engaged.}
13 _{All functions except inverse sinc and digital multipliers engaged.}
Rev. E | Page 7 of 52