AD9851BRSZRL Datasheet, PDF (7/24 Pages) Analog Devices – CMOS 180 MHz DDS/DAC Synthesizer

Tek Run 4.00GS/s Sample
T[
]
 : 208ps
@ : 1.940ns
1
Tek Run 4.00GS/s Sample
T[
]
 : 280ps
@ : 2.668ns
1
AD9851
Ch1 200mV
M 12.5ns Ch 1 –200mV
D 200ps Runs After
TPC 7. Typical CMOS comparator p-p output jitter with
the AD9851 configured as a clock generator, DDS f_OUT =
10.1 MHz, V_S = 5 V, system clock = 180 MHz, 70 MHz LPF.
Graph details the center portion of a rising edge with
scope in delayed trigger mode, 200 ps/div. Cursors show
208 ps p-p jitter.
Tek Run 4.00GS/s Sample
T
[
]
 : 204ps
@ : 3.672ns
1
Ch1 200mV
M 12.5ns Ch 1 –200mV
D 200ps Runs After
TPC 8. Typical CMOS comparator p-p output jitter with the
AD9851 configured as a clock generator, DDS f_OUT = 40.1 MHz,
V_S = 5 V, system clock = 180 MHz, 70 MHz LPF. Graph details
the center portion of a rising edge with scope in delayed
trigger mode, 200 ps/div. Cursors show 204 ps p-p jitter.
Ch1 200mV
M 12.5ns Ch 1 –200mV
D 200ps Runs After
TPC 9. Typical CMOS comparator p-p output
jitter with the AD9851 configured as a clock
generator, DDS f_OUT = 70.1 MHz, V_S = 5 V, system
clock = 180 MHz, 70 MHz LPF. Graph details
the center portion of a rising edge with scope
in delayed trigger mode, 200 ps/div. Cursors
show 280 ps p-p jitter.
–100
–115
AD9851 PHASE NOISE
–120
–125
–130
–135
–140
–145
100
1k
10k
FREQUENCY OFFSET – Hz
100k
TPC 10. Output Phase Noise (5.2 MHz A_OUT), 6 REFCLK
Multiplier Enabled, System Clock = 180 MHz, Reference
Clock = 30 MHz
REV. D
–7–