AD8328 Datasheet, PDF (7/16 Pages) Analog Devices – 5 V Upstream Cable Line Driver

AD8328
5V
V_IN+
V_CC
V_OUT+
AD8328
R_L
V_OUT–
1
2
V_IN
1
2
V_IN
V_IN–
BYP
GND
Figure 4. Characterization Circuit
APPLICATIONS
General Applications
The AD8328 is primarily intended for use as the power amplifier
(PA) in DOCSIS (Data Over Cable Service Interface Specification)
certified cable modems and CATV set-top boxes. The upstream
signal is either a QPSK or QAM signal generated by a DSP, a
dedicated QPSK/QAM modulator, or a DAC. In all cases, the
signal must be low-pass filtered before being applied to the PA in
order to filter out-of-band noise and higher order harmonics from
the amplified signal.
Due to the varying distances between the cable modem and the
head-end, the upstream PA must be capable of varying the output
power by applying gain or attenuation. The ability to vary the
output power of the AD8328 ensures that the signal from the cable
modem will have the proper level once it arrives at the head-end.
The upstream signal path commonly includes a diplexer and cable
splitters. The AD8328 has been designed to overcome losses asso-
ciated with these passive components in the upstream cable path.
Circuit Description
The AD8328 is composed of three analog functions in the power-up
or forward mode. The input amplifier (preamp) can be used
single-ended or differentially. If the input is used in the differential
configuration, it is imperative that the input signals be 180 degrees out
of phase and of equal amplitude. A vernier is used in the input
stage for controlling the fine 1 dB gain steps. This stage then drives
a DAC, which provides the bulk of the AD8328’s attenuation. The
signals in the preamp and DAC gain blocks are differential to
improve the PSRR and linearity. A differential current is fed from
the DAC into the output stage. The output stage maintains 300 Ω
differential output impedance, which maintains proper match to 75 Ω
when used with a 2:1 balun transformer.
SPI Programming and Gain Adjustment
The AD8328 is controlled through a serial peripheral interface
(SPI) of three digital data lines: CLK, DATEN, and SDATA.
Changing the gain requires eight bits of data to be streamed into
the SDATA port. The sequence of loading the SDATA register
begins on the falling edge of the DATEN pin, which activates the
CLK line. With the CLK line activated, data on the SDATA line
is clocked into the serial shift register on the rising edge of the
CLK pulses, most significant bit (MSB) first. The 8-bit data-word
is latched into the attenuator core on the rising edge of the
DATEN line. This provides control over the changes in the
output signal level. The serial interface timing for the AD8328
is shown in Figures 2 and 3. The programmable gain range of
the AD8328 is –28 dB to +31 dB with steps of 1 dB per least
significant bit (LSB). This provides a total gain range of 59 dB.
The AD8328 was characterized with a differential signal on the
input and a TOKO 458PT-1087 2:1 transformer on the output.
The AD8328 incorporates supply current scaling with gain code,
as seen in TPC 12. This allows reduced power consumption when
operating in lower gain codes.
Input Bias, Impedance, and Termination
The V_IN+ and V_IN– inputs have a dc bias level of V_CC/2; therefore
the input signal should be ac-coupled as seen in the typical
application circuit (see Figure 5). The differential input impedance
of the AD8328 is approximately 1.6 kΩ, while the single-ended
input is 800 Ω. The high input impedance of the AD8328 allows
flexibility in termination and properly matching filter networks.
The AD8328 will exhibit optimum performance when driven
with a pure differential signal.
Output Bias, Impedance, and Termination
The output stage of the AD8328 requires a bias of +5 V. The
+5 V power supply should be connected to the center tap of the
output transformer. Also, the V_CC that is being applied to the
center tap of the transformer should be decoupled as seen in the
typical applications circuit (Figure 5).
V_CC
10␮F
Z_IN = 150⍀
V_IN+
165⍀
V_IN–
0.1␮F
0.1␮F
DATEN
SDATA
CLK
TXEN
SLEEP
1k⍀
1k⍀
1k⍀
1k⍀
1k⍀
AD8328
1
2 ^GND
3 ^VCC
4 ^GND
GND
QSOP
GND ²⁰
V_CC ¹⁹
TXEN ¹⁸
RAMP ¹⁷
5
6 ^VIN+
7 ^VIN–
GND
V_OUT+ ¹⁶
V_OUT– ¹⁵
BYP ¹⁴
8 _DATEN
NC ¹³
9 _SDATA
SLEEP ¹²
10 _CLK
GND ¹¹
0.1␮F
0.1␮F
TO DIPLEXER
Z_IN = 75⍀
TOKO 458PT-1087
0.1␮F
REV. 0
Figure 5. Typical Application Circuit
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