 English |
|
|
|
|
|
|
|
| AD7722_15 Datasheet, PDF (7/24 Pages) Analog Devices – 16-Bit, 195 kSPS | |||
| |||
| ◁ |
AD7722
DOE
t15
t16
SDO
Figure 5. Serial Mode Timing for Data Output Enable and Serial Data Output (TSI = Logic Low)
DRDY
CS
RD
DB0âDB15
t17
t18
t19
t25
t20
t24
t21
t22
t23
VALID DATA
Figure 6. Parallel Mode Read Timing
CLKIN
t28 MIN
SYNC, RESET
t27
DVAL
t28 MAX
t26
t29
t30
t31
DRDY
Figure 7. SYNC and RESET Timing, Serial and Parallel Mode
CLKIN
t34
SYNC, RESET
DVAL
DRDY
t36
t35
t37 UNI = 1
t37 UNI = 0
8192 tCLK
512 tCLK
8192 tCLK
512 tCLK
8192 tCLK
t38
512 tCLK
8192 tCLK
Figure 8. Calibration Timing, Serial and Parallel Mode
REV. B
â7â
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese