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AD7476A Datasheet, PDF (7/24 Pages) Analog Devices – 2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70
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AD7476A/AD7477A/AD7478A
Timing Example 1
Having fSCLK = 20 MHz and a throughput of 1 MSPS gives a
cycle time of t2 + 12.5 (1/fSCLK) + tACQ = 1 µs. With t2 = 10 ns min,
this leaves tACQ to be 365 ns. This 365 ns satisfies the requirement
of 250 ns for tACQ. From Figure 3, tACQ is comprised of 2.5 (1/fSCLK)
+ t8 + tQUIET, where t8 = 36 ns max. This allows a value of 204 ns
for tQUIET, satisfying the minimum requirement of 50 ns.
Timing Example 2
Having fSCLK = 5 MHz and a throughput of 315 kSPS gives a
cycle time of t2 + 12.5 (1/fSCLK) + tACQ = 3.174 µs. With t2 =
10 ns min, this leaves tACQ to be 664 ns. This 664 ns satisfies
the requirement of 250 ns for tACQ. From Figure 3, tACQ is
comprised of 2.5 (1/fSCLK) + t8 + tQUIET, t8 = 36 ns max. This
allows a value of 128 ns for tQUIET, satisfying the minimum
requirement of 50 ns. As in this example and with other slower
clock values, the signal may already be acquired before the
conversion is complete, but it is still necessary to leave 50 ns
minimum tQUIET between conversions. In Example 2, the
signal should be fully acquired at approximately Point C in
Figure 3.
CS
SCLK
tCONVERT
t2
t6
1
2
3
4
5
SDATA
THREE-
STATE
t3
Z ZERO
ZERO
t4
ZERO
4 LEADING ZEROS
DB11
t7
DB10
t1
B
13
14
t5
15
16
t8
DB2
DB1
DB0
tQUIET
THREE-STATE
Figure 2. AD7476A Serial Interface Timing Diagram
CS
SCLK
t2
1
2
tCONVERT
3
4
5
B
13
14
12.5(1/fSCLK)
1/THROUGHPUT
C
15
16
t8
tACQ
Figure 3. Serial Interface Timing Example
tQUIET
REV. C
–7–
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