AD7357_08 Datasheet, PDF (7/20 Pages) Analog Devices – Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC

Preliminary Technical Data
AD7357
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V_INA+ 1
V_INA– 2
REF_A 3
REFGND 4
AGND 5
16 V_DRIVE
15 SCLK
AD7357
TOP VIEW
(Not to Scale)
14 SDATA_A
13 SDATA_B
12 DGND
REF_B 6
V_INB– 7
V_INB+ 8
11 AGND
10 CS
9 V_DD
Figure 2.
Table 5. Pin Function Descriptions
Pin
No. Mnemonic
Description
1, 2
VINA-, VINA+
Analog Inputs of ADC A. These analog inputs form a fully differential pair.
3, 6 REFA, REFB
Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the
REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each
reference pin with a 10 µF capacitor. Provided the output is buffered, the on-chip reference can be taken from
these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048 V and
appears at these pins. These pins can also be overdriven by an external reference. The input voltage range for
the external reference is 2.048 V +100 mV to VDD.
4
REFGND
Reference Ground. This is the ground reference point for the reference circuitry on the AD7357. Any external
reference signal should be referred to this REFGND voltage. Decoupling capacitors must be placed between this
pin and the REFA and REFB pins.
5, 11 AGND
Analog Ground. This is the ground reference point for all analog circuitry on the AD7357. All analog input signals
and should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
7, 8
VINB-, VINB+
Analog Inputs of ADC B. These analog inputs form a fully differential pair.
9
VDD
Power Supply Input. The VDD range for the AD7357 is 2.5 V ± 10%. The supply should be decoupled to AGND with
a 0.1 µF capacitor and a 10 µF tantalum capacitor.
10
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7357
and framing the serial data transfer.
12
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7357. This pin should connect
to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
13, 14
SDATAB, SDATAA
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input. 16 SCLK falling edges are required to access the 14 bits of data from the
AD7357. The data simultaneously appears on both data output pins from the simultaneous conversions of both
ADCs. The data stream consists of one leading zero followed by the 14 bits of conversion data followed by a
trailing zero. The data is provided MSB first. If CSis held low for 18 SCLK cycles rather than 16, then two further
trailing zeros appear after the 14 bits of data. If CSis held low for a further 18 SCLK cycles on either SDATAA or
SDATAB , the data from the other ADC follows on the SDATA pin. This allows data from a simultaneous
conversion on both ADCs to be gathered in serial format on either SDATAA or SDATAB.
15
SCLK
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7357. This
clock is also used as the clock source for the conversion process.
16
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage at this pin may be different to that at VDD.
Rev. PrF | Page 7 of 20