AD5764 Datasheet, PDF (7/27 Pages) Analog Devices – Complete, Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC

Preliminary Technical Data
AD5764
TIMING CHARACTERISTICS
AVDD = +11.4 V to +15.75 V, AVSS = −11.4 V to −15.75 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD= 5 V Ext;
DVCC = 2.7 V to 5.5 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter^7,8,9
t1
t2
t3
t4
t5 ¹⁰
t6
t7
t8
t9
t10
t11
t12
t13
t14
t1511,12
t1612
t1712
Limit at TMIN, TMAX
33
13
13
13
13
40
5
0
20
20
5
10
20
12
20
8
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs max
ns min
µs max
ns max
ns min
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24^th SCLK falling edge to SYNC rising edge
Minimum SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to LDAC falling edge
7 _{Guaranteed by design and characterization. Not production tested.}
8 _{All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.}
9 _{See Figure 2, Figure 3, and Figure 4.}
10 _{Stand-alone mode only.}
11 _{Measured with the load circuit of Figure 5.}
12 _{Daisy-chain mode only.}
Rev. PrC 21-Oct-04| Page 7 of 28