AD5762R Datasheet, PDF (7/33 Pages) Analog Devices – Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DACs

Preliminary Technical Data
AD5762R
TIMING CHARACTERISTICS
AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA, REFB= 5 V external;
DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter^{1, 2, 3}
t1
t2
t3
t4
t54
t6
t7
t8
t9
Limit at TMIN, TMAX
33
13
13
13
13
40
2
5
1.4
400
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24^th SCLK falling edge to SYNC rising edge
Minimum SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
t10
10
ns min
LDAC pulse width low
t11
500
ns max LDAC falling edge to DAC output response time
t12
10
µs max DAC output settling time
t13
10
ns min
CLR pulse width low
t14
2
µs max CLR pulse activation time
t155, ⁶
25
ns max SCLK rising edge to SDO valid
t16
13
ns min
SYNC rising edge to SCLK falling edge
t17
2
µs min
SYNC rising edge to DAC output response time (LDAC = 0)
t18
170
ns min
LDAC falling edge to SYNC rising edge
1 _{Guaranteed by design and characterization; not production tested.}
2 _{All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.}
3 _{See Figure 2, Figure 3, and Figure 4.}
4 _{Standalone mode only.}
5 _{Measured with the load circuit of Figure 5.}
6 _{Daisy-chain mode only.}
Rev. PrA | Page 7 of 33