AD5593R Datasheet, PDF (7/34 Pages) Analog Devices – Control and monitoring

AD5593R
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = 2.7 V to
5.5 V, 1.8 V ≤ VLOGIC ≤ VDD; 2.5 V ≤ VREF ≤ VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter¹ Min
Typ
t1
2.5
t2
0.6
t3
1.3
t4
0.6
t5
100
t62
t7
0.6
t8
0.6
t9
1.3
t10
0
t11
0
20 + 0.1CB3
CB3
Max
0.9
300
250
300
400
Unit Conditions/Comments
μs
SCL cycle time
μs
tHIGH, SCL high time
μs
tLOW, SCL low time
μs
tHD,STA, start/repeated start condition hold time
ns
tSU,DAT, data setup time
μs
tHD,DAT, data hold time
μs
tSU,STA, setup time for repeated start
μs
tSU,STO, stop condition setup time
μs
tBUF, bus free time between a stop and a start condition
ns
tR, rise time of SCL and SDA when receiving
ns
tR, rise time of SCL and SDA when receiving (CMOS compatible)
ns
tF, fall time of SDA when transmitting
ns
tF, fall time of SDA when receiving (CMOS compatible)
ns
tF, fall time of SCL and SDA when receiving
ns
tF, fall time of SCL and SDA when transmitting
pF
Capacitive load for each bus line
1 _{Guaranteed by design and characterization; not production tested.}
2 _{A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling}
edge of SCL.
3 _{CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.}
Timing Diagram
SDA
t₉
t₃
t₁₀
t₁₁
t₄
SCL
t₄
START
CONDITION
t₆
t₂
t₅
t₇
t₁
REPEATED
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
t₈
STOP
CONDITION
Rev. B | Page 6 of 33