AD5175 Datasheet, PDF (7/20 Pages) Analog Devices – Single-Channel, 1024-Position, Digital Rheostat with I2C Interface and 50-TP Memory

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5175
V_DD 1
10 ADDR
A 2 ^AD5175 9 SCL
W3
8 SDA
V_SS 4
TOP VIEW
(Not to Scale)
7
RESET
EXT_CAP 5
6 GND
Figure 4. MSOP Pin Configuration
V_DD 1
A2
W3
V_{SS 4}
EXT_CAP 5
AD5175
(EXPOSED
PAD)*
10 ADDR
9 SCL
8 SDA
7 RESET
6 GND
*LEAVE FLOATING OR CONNECTED TO V_SS.
Figure 5. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD
Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
2
A
Terminal A of RDAC. VSS ≤ VA ≤ VDD.
3
W
Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
4
VSS
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors
and 10 μF capacitors.
5
EXT_CAP
External Capacitor. Connect a 1 μF capacitor between EXT_CAP and VSS. This capacitor must have a voltage
rating of ≥7 V.
6
GND
Ground Pin, Logic Ground Reference.
7
RESET
Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory
default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET
to VDD if not used.
8
SDA
Serial Data Line. This pin is used in conjunction with the SCL line to clock data into or out of the 16-bit input
registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external
pull-up resistor.
9
SCL
Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 16-bit
input registers.
10
ADDR
Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 6).
EPAD Exposed Pad Leave floating or connected to VSS
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