AD15700 Datasheet, PDF (7/44 Pages) Analog Devices – 1 MSPS 16-/14-Bit Analog I/O Port

AD15700
14-BIT DAC TIMING CHARACTERISTICS1, 2 (VDD = 5 V, ؎5%, VREF = 2.5 V, AGND = DGND = 0 V. All Specifications
T_A = T_MIN to T_MAX, unless otherwise noted).
Parameter
Limit at T_MIN, T_MAX All Versions
Unit
Description
f_SCLK
25
t₁
40
t₂
20
t₃
20
t₄
15
t₅
15
t₆
35
t₇
20
t₈
15
t₉
0
t₁₀
30
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
CS_DAC Low to SCLK High Setup
CS_DAC High to SCLK High Setup
SCLK High to CS_DAC Low Hold Time
SCLK High to CS_DAC High Hold Time
Data Setup Time
Data Hold Time
CS_DAC High Time between Active Periods
NOTES
1_{Guaranteed by design. Not production tested.}
2_{Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90%}
of 3 V and timed from a voltage level of 1.6 V).
Specifications subject to change without notice.
SCLK
CS_DAC
DIN
t₁
t₆
t₄
t₂
t₃
t₅
t₇
t₁₀
t₈
t₉
DB13
DB0
Figure 3. Timing Diagram
REV. A
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