ADUC702X Datasheet, PDF (69/80 Pages) Analog Devices – Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU

Preliminary Technical Data
ADuC702x Series
The counter can be formatted as plain 32-bit value or as
Hours:Minutes:Seconds:Hundreths.
Timer 2 can be used to start ADC conversions as shown in the
block diagram Figure 30..
Timer2 interface consists in four MMRS:
- T2LD and T2VAL are 32-bit registers and hold 32-bit
unsigned integers. T2VAL is read-only.
- T2CLRI is an 8-bit register. Writing any value to this register
will clear the timer2 interrupt.
- T2CON is the configuration MMR described in Table 62
below.
32.768kHz
Oscillator
32-bit Load
Prescaler
/ 1, 16, 256
or 32768
Timer2IRQ
32-bit Up/Down Counter
ADC conversion
Timer2 Value
Figure 30:timer 2 block diagram
Table 62: T2CON MMR Bit Descriptions
Bit
Description
31-9 Reserved
8
Count up:
Set by user for timer 2 to count up
Cleared by user for timer 2 to count down. by default
7
Timer2 enable bit:
Set by user to enable timer 2
Cleared by user to disable timer 2. by default.
6
Timer 2 mode:
Set by user to operate in periodic mode
Cleared by user to operate in free-running mode. Default mode
5-4
Format:
00
Binary
01
Reserved
10
Hr:Min:Sec:Hundredths – 23 hours to 0 hour
11
Hr:Min:Sec:Hundredths – 255 hours to 0 hour
3-0
Prescale:
0000
Source clock / 1 by default
0100
Source clock / 16
1000
Source clock / 256 expected for format 2 and 3
1111
Source clock / 32768
Timer3 - Watchdog Timer
Timer3 has two modes of operation, normal mode and
watchdog mode. The Watchdog timer is used to recover from
an illegal software state. Once enabled it requires periodic
servicing to prevent it from forcing a reset of the processor.
Normal mode:
The Timer3 in normal mode is identical to Timer0 except for
the clock source and the count-up functionality. The clock
source is 32kHz from the PLL and can be scaled by a factor of 1,
16 or 256.
16-bit Load
32.768kHz
Prescaler
/ 1, 16 or 256
16-bit Up/Down Counter
Watchdog Reset
Timer3IRQ
Timer3 Value
Figure 31:timer 3 block diagram
Watchdog mode:
Watchdog mode is entered by setting bit 5 in T3CON MMR.
Timer3 decrements from the value present in T3LD Register
until zero. T3LD is used as timeout. The timeout can be 512
seconds maximum, using the maximum prescaler, /256, full-
scale in T3LD. Timer3 is clocked by the internal 32kHZ crystal
when operating in the Watchdog mode.
If the timer reaches 0, a reset or an interrupt occurs, depending
on bit 1 in T3CON register. To avoid reset or interrupt, any
Rev. PrB | Page 69 of 80