AD9531 Datasheet, PDF (68/88 Pages) Analog Devices – 3-Channel Clock Generator, 24 Outputs

AD9531
Data Sheet
Registers for PLL1 Group 1C Outputs, OUT1_8x to OUT1_9x—Register 0x011A to Register 0x011C
Table 61. PLL1 Group 1C Outputs
Address Bits
Bit Name
0x011A [D7:D0] D1C [7:0]
0x011B [D7:D6] Unused
[D5:D3] Logic mode [2:0]
[D2:D1] Polarity [1:0]
D0
Power-down
0x011C [D7:D6] Unused
[D5:D3] Logic mode [2:0]
[D2:D1] Polarity [1:0]
D0
Power-down
Description
D1C divider Bit D7 (MSB) to Bit D0 (LSB). The divide factor is the value of D1C [7:0] + 1. D1C powers
down when all four of the associated output drivers power down, whether via the power-down bit
or via the logic mode bits.
Unused.
Configure OUT1_8x output driver as follows:
000: disabled.
001: HSTL.
010: undefined.
011: undefined.
100: 1.8 V CMOS, OUT1_8P active, OUT1_8N active.
101: 1.8 V CMOS, OUT1_8P active, OUT1_8N disabled.
110: 1.8 V CMOS, OUT1_8P disabled, OUT1_8N active.
111: undefined.
Configure OUT1_8 polarity (applies to CMOS, only) as follows:
00: OUT1_8P normal, OUT1_8N inverted.
01: OUT1_8P normal, OUT1_8N normal.
10: OUT1_8P inverted, OUT1_8N inverted.
11: OUT1_8P inverted, OUT1_8N normal.
0: OUT1_8x driver active.
1: OUT1_8x driver powered down.
Unused.
Configure the OUT1_9x output driver as follows:
000: disabled.
001: HSTL.
010: undefined.
011: undefined.
100: 1.8 V CMOS, OUT1_9P active, OUT1_9N active.
101: 1.8 V CMOS, OUT1_9P active, OUT1_9N disabled.
110: 1.8 V CMOS, OUT1_9P disabled, OUT1_9N active.
111: undefined.
Configure OUT1_9x polarity as follows (applies to CMOS only):
00: OUT1_9P normal, OUT1_9N inverted.
01: OUT1_9P normal, OUT1_9N normal.
10: OUT1_9P inverted, OUT1_9N inverted.
11: OUT1_9P inverted, OUT1_9N normal.
0: OUT1_9x driver active.
1: OUT1_9x driver powered down.
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