AD7124-8_17 Datasheet, PDF (68/93 Pages) Analog Devices – 8-Channel, Low Noise, Low Power, 24-Bit Sigma-Delta ADC with PGA and Reference

Data Sheet
AD7124-8
The positive (AINP) and negative (AINM) analog inputs can be
separately checked for overvoltages and undervoltages. The
AINP_OV_ERR_EN and AINP_UV_ERR_EN bits in the
ERROR_EN register enable the overvoltage/undervoltage
diagnostics respectively. An overvoltage is flagged when the
voltage on AINP exceeds AVDD while an undervoltage is flagged
when the voltage on AINP goes below AVSS. Similarly, an
overvoltage/undervoltage check on the negative analog input
pin is enabled using the AINM_OV_ERR_EN and AINM_UV_
ERR_EN bits in the ERROR_EN register. The error flags are
AINP_OV_ERR, AINP_UV_ERR, AINM_OV_ERR, and
AINM_UV_ERR in the error register.
When this function is enabled, the corresponding flags may be
set in the error register. Therefore, the user must read the error
register when the overvoltage/undervoltage checks are enabled
to ensure that the flags are reset to 0.
POWER SUPPLY MONITORS
Along with converting external voltages, the ADC can monitor
the voltage on the AVDD pin and the IOVDD pin. When the
inputs of AVDD to AVSS or IOVDD to DGND are selected, the
voltage (AVDD to AVSS or IOVDD to DGND) is internally
attenuated by 6, and the resulting voltage is applied to the Σ-Δ
modulator. This is useful because variations in the power supply
voltage can be monitored.
LDO MONITORING
There are several LDO checks included on the AD7124-8. Like
the external power supplies, the voltage generated by the analog
and digital LDOs are selectable as inputs to the ADC. In addition,
the AD7124-8 can continuously monitor the LDO voltages.
Power Supply Monitor
The voltage generated by the ALDO and DLDO can be
monitored by enabling the ALDO_PSM_ERR_EN bit and the
DLDO_PSM_ERR_EN bit, respectively, in the ERROR_EN
register. When enabled, the output voltage of the LDO is
continuously monitored. If the ALDO voltage drops below
1.6 V, the ALDO_PSM_ERR flag is asserted. If the DLDO
voltage drops below 1.55 V, the DLDO_PSM_ERR flag is
asserted. The bit remains set until the corresponding LDO
voltage recovers. However, the bit is only cleared when the
error register is read.
OVERVOLTAGE
COMPARATOR
ALDO
1.6V
SET IF ALDO OUTPUT VOLTAGE IS
LESS THAN 1.6V
Figure 123. Analog LDO Monitor
OVERVOLTAGE
COMPARATOR
DLDO
1.55V
SET IF DLDO OUTPUT VOLTAGE IS
LESS THAN 1.55V
Figure 124. Digital LDO Monitor
The AD7124-8 can also test the circuitry used for the power
supply monitoring. When the ALDO_PSM_TRIP_TEST_EN or
DLDO_PSM_TRIP_TEST_EN bits are set, the input to the test
circuitry is tied to GND rather than the LDO output. Set the
corresponding ALDO_PSM_ERR or DLDO_PSM_ERR bit.
LDO Capacitor Detect
The analog and digital LDOs require an external decoupling
capacitor of 0.1 µF. The AD7124-8 can check for the presence of
this decoupling capacitor. Using the LDO_CAP_CHK bits in
the ERROR_EN register, the LDO being checked is turned off
and the voltage at the LDO output is monitored. If the voltage
falls, this is considered a fail and the LDO_CAP_ERR bit in the
error register is set.
Only the analog LDO or digital LDO can be tested for the
presence of the decoupling capacitor at any one time. This test
also interferes with the conversion process.
The circuitry used to check for missing decoupling capacitors
can also be tested by the AD7124-8. When the LDO_CAP_
CHK_TEST_EN bit in the ERROR_EN register is set, the
decoupling capacitor is internally disconnected from the LDO,
forcing a fault condition. Therefore, when the LDO capacitor
test is performed, a fault condition is reported, that is, the
LDO_CAP_ERR bit in the error register is set.
MCLK COUNTER
A stable master clock is important as the output data rate, filter
settling time, and the filter notch frequencies are dependent on
the master clock. The AD7124-8 allows the user to monitor the
master clock. When the MCLK_CNT_EN bit in the ERROR_EN
register is set, the MCLK_COUNT register increments by 1 every
131 master clock cycles. The user can monitor this register over
a fixed period of time. The master clock frequency can be
determined from the result in the MCLK_COUNT register.
The MCLK_COUNT register wraps around after it reaches its
maximum value.
SPI SCLK COUNTER
The SPI SCLK counter counts the number of SCLK pulses used
in each read and write operation. CS must frame every read and
write operation when this function is used. All read and write
operations are multiples of eight SCLK pulses (8, 16, 32, 40, 48).
If the SCLK counter counts the SCLK pulses and the result is not a
multiple of eight, an error is flagged; the SPI_SCLK_CNT_ERR bit
in the error register is set. If a write operation is being performed
and the SCLK contains an incorrect number of SCLK pulses,
the value is not written to the addressed register and the write
operation is aborted.
The SCLK counter is enabled by setting the SPI_SCLK_
CNT_ERR_EN bit in the ERROR_EN register.
Rev. D | Page 67 of 92