AD9520-0 Datasheet, PDF(64/84 Page) Analog Devices – 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

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AD9520-0 Datasheet, PDF (64/84 Pages) Analog Devices – 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

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AD9520-0

Addr

(Hex)

193

194

Parameter

Divider 1 (PECL)

195

Bit 7 (MSB)

Divider 1

bypass

196 Divider 2 (PECL)

197

Divider 2

bypass

198

199 Divider 3 (PECL)

Bit 6

Bit 5

Divider 1 low cycles

Divider 1

ignore

SYNC

Divider 1

force

high

Unused

Bit 4

Divider 1

start high

Bit 3

Unused

Divider 2 low cycles

Divider 2

ignore

SYNC

Divider 2

force

high

Unused

Divider 2

start high

Unused

Divider 3 low cycles

Bit 2

Bit 1

Divider 1 high cycles

Divider 1

phase offset

Channel 1

power-

down

Channel 1

direct-to-

output

Divider 2 high cycles

Divider 2

phase offset

Channel 2

power-

down

Channel 2

direct-to-

output

Divider 3 high cycles

Bit 0 (LSB)

Disable

Divider 1

DCC

Disable

Divider 2

DCC

19A

Divider 3

bypass

19B

19C

1DF

VCO Divider and CLK Input

1E0 VCO divider

Divider 3

ignore

SYNC

Divider 3

force

high

Unused

Divider 3

start high

Unused

Divider 3

phase offset

Channel 3 Channel 3

power- direct-to-

down

output

Disable

Divider 3

DCC

Unused

VCO divider

1E1 Input CLKs

Unused

1E2

22A

System

230 Power-down

and SYNC

231

Update All Registers

232 IO_UPDATE

233

9FF

EEPROM Buffer Segment

A00 EEPROM

Buffer Segment

Unused

(default = 1)

Power -

down

clock

input

section

Power-

down VCO

clock

interface

Unused

Power-

down

VCO

and CLK

Select

VCO or CLK

Bypass VCO

divider

Unused

Disable

power-on

SYNC

Unused

Power-

down

SYNC

Power-

down

distribution

reference

Unused

Soft

SYNC

IO_UPDATE

(self-clearing)

EEPROM Buffer Segment Register 1 (default: number of bytes for Group 1)

A01 EEPROM

Buffer Segment

A02 EEPROM

Buffer Segment

A03 EEPROM

Buffer Segment

A04 EEPROM

Buffer Segment

EEPROM Buffer Segment Register 2 (default: Bits[15:8] of starting register address for Group 1)

EEPROM Buffer Segment Register 3 (default: Bits[7:0] of starting register address for Group 1)

EEPROM Buffer Segment Register 4 (default: number of bytes for Group 2)

EEPROM Buffer Segment Register 5 (default: Bits[15:8] of starting register address for Group 2)

Rev. 0 | Page 64 of 84

Default

Value

(Hex)

▷