ADUC7033_15 Datasheet, PDF (63/140 Pages) Analog Devices – Integrated, Precision Battery Sensor for Automotive

ADuC7033
Self-Calibration
In self (offset or gain) calibration, the ADC generates its
calibration coefficient based on an internally generated 0 V in
the case of self-offset calibration, and full-scale voltage in the
case of self-gain calibration. It should be emphasized that ADC
self-calibrations correct for offset and gain errors within the
ADC. Self-calibrations cannot compensate for other external
errors in the system, for example, shunt resistor tolerance/drift,
external offset voltages, and so on.
Note that in self-calibration mode, ADC0GN must first contain
the values for PGA = 1, before a calibration scheme is started.
System Calibration
to use the calibration registers is to let the ADC calculate the
values required as part of the ADC automatic calibration modes.
A factory, or end-of-line calibration, for the I-ADC is a two-
step procedure.
1. Apply 0 A current. Configure the ADC in the required
PGA setting, and so on, and write to ADCMDE[2:0] to
perform a system zero-scale calibration. This writes a new
offset calibration value into ADC0OF.
2. Apply a full-scale current for the selected PGA setting.
Write to ADCMDE to perform a system full-scale
calibration. This writes a new gain calibration value into
ADC0GN.
In system (offset or gain) calibration, the ADC generates
its calibration coefficient based on an externally generated
zero-scale voltage (in the case of system offset calibration) and
full-scale voltage (in the case of system gain calibration), which
are applied to the external ADC input for the duration of the
calibration cycle.
The duration of an offset calibration is a single conversion cycle
(3/fADC with chop off, 2/fADC with chop on) before returning the
ADC to idle mode. A gain calibration is a two-stage process
and, therefore, takes twice as long as an offset calibration cycle.
When a calibration cycle is initiated, any ongoing ADC conver-
sion is immediately halted, the calibration is automatically carried
out at an ADC update rate programmed into ADCFLT, and the
ADC is always returned to idle after any calibration cycle. It is
strongly recommended that ADC calibration is initiated at as
low an ADC update rate as possible (high SF value in ADCFLT)
to minimize the impact of ADC noise during calibration.
Using the Offset and Gain Calibration
If the Chop Enable Bit ADCFLT[15] is enabled, then internal
ADC offset errors are minimized and an offset calibration may
not be required. If chopping is disabled however, an initial offset
calibration is required and may need to be repeated, particularly
after a large change in temperature.
A gain calibration, particularly in the context of the I-ADC
(with internal PGA), may need to be carried out at all relevant
system gain ranges depending on system accuracy requirements.
If it is not possible to apply an external full-scale current on all
gain ranges, then it is possible to apply a lower current and scale
the result produced by the calibration. For example, apply a 50%
current and then divide the ADC0GN value produced-by-two
and write this value back into ADC0GN. Note that there is a
lower limit to the input signal that can be applied for a system
calibration because ADC0GN is only a 16-bit register. The input
span (difference between the system zero-scale value and system
full-scale value) should be greater than 40% of the nominal full-
scale-input range, that is, >40% of VREF/gain.
The on-chip Flash/EE memory can be used to store multiple
calibration coefficients. These can be copied by user code
directly into the relevant calibration registers, as appropriate,
based on the system configuration. In general, the simplest way
Understanding the Offset and Gain Calibration Registers
The output of the average block in the ADC signal flow (described
previously from the ADC Sinc3 Digital Filter Response section
to the Using the Offset and Gain Calibration section) can be
considered a fractional number with a span for a ±full-scale input
of approximately ±0.75. The span is less than ±1.0 because there is
attenuation in the modulator to accommodate some overrange
capacity on the input signal. The exact value of the attenuation
varies slightly from part to part, because of manufacturing
tolerances.
The offset coefficient is read from the ADC0OF calibration
register. This value is a 16-bit, twos complement number. The
range of this number, in terms of the signal chain, is effectively
±1.0. Therefore, 1 LSB of the ADC0OF register is not the same
as 1 LSB of ADC0DAT.
A positive value of ADC0OF indicates that when offset is
subtracted from the output of the filter, a negative value is added.
The nominal value of this register is 0x0000, indicating zero
offset is to be removed. The actual offset of the ADC can vary
slightly from part to part and at different PGA gains. The offset
within the ADC is minimized if the chopping mode is active
(ADCFLT[15] = 1).
The gain coefficient is a unitless scaling factor. The 16-bit value
in this register is divided by 16,384 and then multiplied by the
offset corrected value. The nominal value of this register equals
0x5555, corresponding to a multiplication factor of 1.3333. This
scales the nominal ±0.75 signal to produce a full-scale output
signal of ±1.0, which is checked for overflow/underflow and
converted to twos complement or unipolar mode as appropriate
before being output to the data register.
The actual gain, and the required scaling coefficient for zero
gain error, varies slightly from part to part, at different PGA
settings, and in normal/low power mode. The value down-
loaded into ADC0GN at power-on-reset represents the scaling
factor for a PGA gain = 1. There is some level of gain error if
this value is used at different PGA settings. User code can
overwrite the calibration coefficients or run ADC calibrations
to correct the gain error at the current PGA setting.
Rev. B | Page 63 of 140