ADAU1442 Datasheet, PDF (63/92 Pages) Analog Devices – SigmaDSP Digital Audio Processor

ADAU1442/ADAU1445/ADAU1446
Watchdog Modes and Settings
Watchdog Registers (Address 0xE210 to Address 0xE212)
Table 44. Register Details of Watchdog Registers
Address
Decimal
Hex
Register
57872
E210 Watchdog enable
57873
E211 Watchdog Value 1
57874
E212 Watchdog Value 2
Function
1-bit enable register for watchdog timer
16 MSBs of the watchdog maximum count value
16 LSBs of the watchdog maximum count value
Default
0
0
0
A program counter watchdog is used when the core performs
block processing (which can span several samples). The watchdog
flags an error if the program counter reaches the 32-bit value set in
the watchdog value registers. This value consists of two consecutive
16-bit register locations. The error flag sends a high signal to one of
the multipurpose pins. The watchdog function must be enabled
by setting the single-bit register at Location 57872 high.
The register configuration for the watchdog counter is as follows:
• Watchdog enable is a 1-bit enable.
• Watchdog Value 1 is the 16 MSBs of the watchdog
maximum count value.
• Watchdog Value 2 is the 16 LSBs of the watchdog
maximum count value.
Table 45. Bit Descriptions of Register 0xE210
Bit Position Description
[15:1]
Reserved
0
Watchdog enable
Default
0
Watchdog Error Sticky Register (Address 0xE226)
Table 46. Bit Descriptions of Register 0xE226
Bit Position Description
[15:1]
Reserved
0
Watchdog error sticky (read only)
Default
0
This single-bit watchdog error flag goes high when an error occurs.
It can optionally be sent to an MP pin, as described in the
Multipurpose Pin Control Registers (Address 0xE204 to
Address 0xE20F) section. For example, the error flag can
connect to an interrupt pin on a microcontroller in the system.
It resets to 0 when the watchdog enable is reset to 0.
CRC and Watchdog Mute Register (Address 0xE227)
Table 47. Bit Descriptions of Register 0xE227
Bit
Position
Description
[15:2]
Reserved.
1
A CRC error mutes the core automatically.
0
A watchdog error mutes the core
automatically.
Default
0
0
This 2-bit register causes a CRC or watchdog error to
automatically mute the core. The default value is off.
Rev. C | Page 63 of 92