ADSST-21161NKCA100 Datasheet, PDF (6/28 Pages) Analog Devices – SHARC® Melody UltraAudio Processor

ADSST-SHARC-Melody-Ultra
The SHARC Melody Ultra continues the SHARC’s industry-
leading standards of integration for DSPs, combining a high
performance 32-bit DSP core with integrated, on-chip system
features. These features include a 1 Mbit dual-ported SRAM
memory, a host processor interface, an I/O processor that sup-
ports 14 DMA channels, four serial ports, two link ports, an
SDRAM controller, an SPI interface, an external parallel bus,
and glueless multiprocessing.
Figure 2 illustrates the following architectural features:
• Two processing elements, each made up of an ALU, multi-
plier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core proces-
sor cycle
• Interval timer
• On-chip SRAM (1 Mbit)
• SDRAM controller for glueless interface to SDRAMs
• External port that supports
• Interfacing to off-chip memory peripherals
• Glueless multiprocessing for six SHARC Melody Ultra
processors
• Host port read/write of IOP registers
• DMA controller
• Four serial ports
• Two link ports
• SPI compatible interface
• JTAG test access port
• 12 general-purpose I/O pins
Figure 4 shows a typical single-processor system. A multiproc-
essing system appears in Figure 7.
SHARC MELODY ULTRA FAMILY CORE
ARCHITECTURE
The SHARC Melody Ultra includes the following architectural
features of the ADSP-2116x family core:
SIMD Computational Engine
The SHARC Melody Ultra contains two computational process-
ing elements that operate as a Single Instruction Multiple Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY, and each contains an ALU, multiplier, shifter, and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both proc-
essing elements, but each processing element operates on
different data. This architecture is efficient at executing math-
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform single-cycle
instructions. The three units within each processing element are
arranged in parallel, maximizing computational throughput.
Single multifunction instructions execute parallel ALU and
multiplier operations. In SIMD mode, the parallel ALU and
multiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision float-
ing-point, 40-bit extended precision floating-point, and
32-bit fixed-point data formats.
Table 1. Benchmarks (at 100 MHz)
Benchmark Algorithm
Speed (at 100 MHz)
1024 Point Complex FFT
(Radix 4, with Reversal)¹
171 µs
FIR Filter (per Tap)¹
5 ns
IIR Filter (per Biquad)¹
40 ns
Matrix Multiply (Pipelined)
[3 × 3] • [3 × 1]
30 ns
[4 × 4] • [4 × 1]
37 ns
Divide (y/x)
60 ns
Inverse Square Root
40 ns
DMA Transfers
800 Mbytes/s
1_{Assumes two filters in multichannel SIMD mode}
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