ADG936R_15 Datasheet, PDF (6/17 Pages) Analog Devices – CMOS, 1.65 V to 2.75 V, Dual SPDT

Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG936/ADG936-R
RFCA 1
20 GND
V_DD 2
19 INA
GND 3 _ADG936 18 GND
RF1A 4 ADG936-R 17 RF2A
GND 5 TOP VIEW 16 GND
GND 6 ^{(Not to Scale)} 15 GND
RF1B 7
14 RF2B
GND 8
13 GND
GND 9
12 INB
RFCB 10
11 GND
Figure 5. 20-Lead TSSOP (RU-20)
GND 1
RF1A 2
GND 3
GND 4
RF1B 5
ADG936
ADG936-R
TOP VIEW
(Not to Scale)
15 GND
14 RF2A
13 GND
12 GND
11 RF2B
NOTES
1. EXPOSED PAD TIED TO SUBSTATE, GND.
Figure 6. 20-Lead 4 mm × 4 mm LFCSP (CP-20-1)
Table 4. Pin Function Descriptions
Pin No.
20-Lead
TSSOP
20-Lead
LFCSP
Mnemonic
1
18
RFCA
2
19
VDD
3, 5, 6, 8, 9,
11, 13, 15,
16, 18, 20
4
7
10
12
14
17
19
1, 3, 4, 6, 7,
9, 12, 13,
15, 17, 20
2
5
8
10
11
14
16
EP
GND
RF1A
RF1B
RFCB
INB
RF2B
RF2A
INA
EP
Description
Common RF Port for Switch A.
Power Supply Input. These parts can operate from 1.65 V to 2.75 V. VDD should be decoupled
to GND.
Ground Reference Point for All Circuitry on the Part.
RF1A Port.
RF1B Port.
Common RF Port for Switch B.
Logic Control Input.
RF2B Port.
RF2A Port.
Logic Control Input.
Exposed Pad. The exposed pad must be tied to substrate, GND.
Rev. B | Page 5 of 16