ADCLK948 Datasheet, PDF (6/12 Pages) Analog Devices – Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer

ADCLK948
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK0 1
CLK0 2
V_REF0 3
V_T0 4
CLK1 5
CLK1 6
V_T1 7
V_REF1 8
PIN 1
INDICATOR
ADCLK948
TOP VIEW
(Not to Scale)
24 Q2
23 Q2
22 Q3
21 Q3
20 Q4
19 Q4
18 Q5
17 Q5
NOTES
1. NC = NO CONNECT.
2. EPAD MUST BE SOLDERED TO V_EE POWER PLANE.
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
1
CLK0
2
CLK0
3
VREF0
4
VT0
5
CLK1
6
CLK1
7
VT1
8
VREF1
9
NC
10, 15, 16, 25, 26, 31
11, 12
VCC
Q7, Q7
13, 14
Q6, Q6
17, 18
Q5, Q5
19, 20
Q4, Q4
21, 22
Q3, Q3
23, 24
Q2, Q2
27, 28
Q1, Q1
29, 30
Q0, Q0
32
IN_SEL
(33)
EPAD
Description
Differential Input (Positive) 0.
Differential Input (Negative) 0.
Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs.
Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0 inputs.
Differential Input (Positive) 1.
Differential Input (Negative) 1.
Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1 inputs.
Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs.
No Connection.
Positive Supply Pin.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs.
EPAD must be connected to VEE.
Rev. 0 | Page 6 of 12