AD9856_15 Datasheet, PDF (6/36 Pages) Analog Devices – CMOS 200 MHz Quadrature Digital Upconverter

AD9856
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
TxENABLE 1
D11 2
D10 3
DVDD 4
DGND 5
D9 6
D8 7
D7 8
D6 9
DVDD 10
DGND 11
D5 ¹²
PIN 1
IDENTIFIER
AD9856
TOP VIEW
(Not to Scale)
13 14 15 16 17 18 19 20 21 22 23 24
36 _{CA DATA}
35 CA ENABLE
34 PLL SUPPLY
33 _{PLL FILTER}
32 PLL GND
31 _AGND
30 I_OUT
29 I_OUTB
28 AGND
27 AVDD
26 DAC REF BYPASS
25 DAC R_SET
NC = NO CONNECT
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Pin Function
1
TxENABLE
Input Pulse that Synchronizes the
Data Stream
2
D11
Input Data (Most Significant Bit)
3
D10
Input Data
4, 10, 21, 44 DVDD
Digital Supply Voltage
5, 11, 20, 43 DGND
Digital Ground
6 to 9
D9 to D6
Input Data
12 to 16
D5 to D1
Input Data
17
D0
Input Data (Least Significant Bit)
18, 19, 22 NC
No Internal Connection
23, 28, 31 AGND
Analog Ground
24
BG REF
No External Connection¹
BYPASS
25
DAC RSET
RSET Resistor Connection
26
DAC REF
No External Connection
1
BYPASS
27
AVDD
Analog Supply Voltage
29
IOUTB
Complementary Analog Current
Output of the DAC
30
IOUT
True Analog Current Output of DAC
Pin No.
32
33
34
35
36
37
38
39
40
41
42
45
46
47
48
Mnemonic
PLL GND
PLL FILTER
PLL SUPPLY
CA ENABLE
CA DATA
CA CLK
CS
SDO
SDIO
SCLK
SYNC I/O
PS0
PS1
REFCLK
RESET
Pin Function
PLL Ground
PLL Loop Filter Connection
PLL Voltage Supply
Cable Driver Amp Enable
Cable Driver Amp Data
Cable Driver Amp Clock
Chip Select
Serial Data Output
Serial Port I/O
Serial Port Clock
Performs I/O Synchronization
Profile Select 0
Profile Select 1
Reference Clock Input
Master Reset
1 _{In most cases, optimal performance is achieved with no external connection. For extremely noisy environments, BG REF BYPASS can be bypassed with up to a 0.1 µF}
capacitor to AGND (Pin 23). DAC REF BYPASS can be bypassed with up to a 0.1 µF capacitor to AVDD (Pin 27).
Rev. C | Page 6 of 36